diff options
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/alpha_cpu.hh | 34 | ||||
-rw-r--r-- | src/cpu/o3/alpha_cpu_impl.hh | 117 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 12 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/thread_state.hh | 31 |
5 files changed, 98 insertions, 102 deletions
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh index 588b11724..3449454bd 100644 --- a/src/cpu/o3/alpha_cpu.hh +++ b/src/cpu/o3/alpha_cpu.hh @@ -96,7 +96,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Reads this CPU's ID. */ virtual int readCpuId() { return cpu->cpu_id; } - virtual TranslatingPort *getMemPort() { return thread->port; } + virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } #if FULL_SYSTEM /** Returns a pointer to the system. */ @@ -116,7 +116,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> { return thread->kernelStats; } #else /** Returns a pointer to this thread's process. */ - virtual Process *getProcessPtr() { return thread->process; } + virtual Process *getProcessPtr() { return thread->getProcessPtr(); } #endif /** Returns this thread's status. */ virtual Status status() const { return thread->status(); } @@ -170,7 +170,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> virtual void profileSample(); #endif /** Returns this thread's ID number. */ - virtual int getThreadNum() { return thread->tid; } + virtual int getThreadNum() { return thread->readTid(); } /** Returns the instruction this thread is currently committing. * Only used when an instruction faults. @@ -207,14 +207,14 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Reads this thread's PC. */ virtual uint64_t readPC() - { return cpu->readPC(thread->tid); } + { return cpu->readPC(thread->readTid()); } /** Sets this thread's PC. */ virtual void setPC(uint64_t val); /** Reads this thread's next PC. */ virtual uint64_t readNextPC() - { return cpu->readNextPC(thread->tid); } + { return cpu->readNextPC(thread->readTid()); } /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); @@ -230,12 +230,12 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Reads a miscellaneous register. */ virtual MiscReg readMiscReg(int misc_reg) - { return cpu->readMiscReg(misc_reg, thread->tid); } + { return cpu->readMiscReg(misc_reg, thread->readTid()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->tid); } + { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } /** Sets a misc. register. */ virtual Fault setMiscReg(int misc_reg, const MiscReg &val); @@ -257,7 +257,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Returns if the thread is currently in PAL mode, based on * the PC's value. */ virtual bool inPalMode() - { return TheISA::PcPAL(cpu->readPC(thread->tid)); } + { return TheISA::PcPAL(cpu->readPC(thread->readTid())); } #endif // Only really makes sense for old CPU model. Lots of code // outside the CPU still checks this function, so it will @@ -279,7 +279,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Executes a syscall in SE mode. */ virtual void syscall(int64_t callnum) - { return cpu->syscall(callnum, thread->tid); } + { return cpu->syscall(callnum, thread->readTid()); } /** Reads the funcExeInst counter. */ virtual Counter readFuncExeInst() { return thread->funcExeInst; } @@ -323,21 +323,21 @@ class AlphaFullCPU : public FullO3CPU<Impl> Fault translateInstReq(RequestPtr &req) { int tid = req->getThreadNum(); - return this->thread[tid]->process->pTable->translate(req); + return this->thread[tid]->getProcessPtr()->pTable->translate(req); } /** Translates data read request in syscall emulation mode. */ Fault translateDataReadReq(RequestPtr &req) { int tid = req->getThreadNum(); - return this->thread[tid]->process->pTable->translate(req); + return this->thread[tid]->getProcessPtr()->pTable->translate(req); } /** Translates data write request in syscall emulation mode. */ Fault translateDataWriteReq(RequestPtr &req) { int tid = req->getThreadNum(); - return this->thread[tid]->process->pTable->translate(req); + return this->thread[tid]->getProcessPtr()->pTable->translate(req); } #endif @@ -492,14 +492,14 @@ class AlphaFullCPU : public FullO3CPU<Impl> #if FULL_SYSTEM // @todo: Fix this LL/SC hack. - if (req->flags & LOCKED) { - if (req->flags & UNCACHEABLE) { - req->result = 2; + if (req->getFlags() & LOCKED) { + if (req->getFlags() & UNCACHEABLE) { + req->setScResult(2); } else { if (this->lockFlag) { - req->result = 1; + req->setScResult(1); } else { - req->result = 0; + req->setScResult(0); return NoFault; } } diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh index 7f3d91640..2debe074b 100644 --- a/src/cpu/o3/alpha_cpu_impl.hh +++ b/src/cpu/o3/alpha_cpu_impl.hh @@ -32,7 +32,7 @@ #include "base/cprintf.hh" #include "base/statistics.hh" #include "base/timebuf.hh" -#include "cpu/checker/exec_context.hh" +#include "cpu/checker/thread_context.hh" #include "sim/sim_events.hh" #include "sim/stats.hh" @@ -77,6 +77,20 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) i, params->mem); this->thread[i]->setStatus(ThreadContext::Suspended); + +#if !FULL_SYSTEM + /* Use this port to for syscall emulation writes to memory. */ + Port *mem_port; + TranslatingPort *trans_port; + trans_port = new TranslatingPort(csprintf("%s-%d-funcport", + name(), i), + params->workload[i]->pTable, + false); + mem_port = params->mem->getPort("functional"); + mem_port->setPeer(trans_port); + trans_port->setPeer(mem_port); + this->thread[i]->setMemPort(trans_port); +#endif //usedTids[i] = true; //threadMap[i] = i; } else { @@ -108,10 +122,25 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) #if FULL_SYSTEM // Setup quiesce event. - this->thread[i]->quiesceEvent = - new EndQuiesceEvent(tc); - this->thread[i]->lastActivate = 0; - this->thread[i]->lastSuspend = 0; + this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); + + Port *mem_port; + FunctionalPort *phys_port; + VirtualPort *virt_port; + phys_port = new FunctionalPort(csprintf("%s-%d-funcport", + cpu->name(), tid)); + mem_port = system->physmem->getPort("functional"); + mem_port->setPeer(phys_port); + phys_port->setPeer(mem_port); + + virt_port = new VirtualPort(csprintf("%s-%d-vport", + cpu->name(), tid)); + mem_port = system->physmem->getPort("functional"); + mem_port->setPeer(virt_port); + virt_port->setPeer(mem_port); + + this->thread[i]->setPhysPort(phys_port); + this->thread[i]->setVirtPort(virt_port); #endif // Give the thread the TC. this->thread[i]->tc = tc; @@ -120,9 +149,8 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) this->threadContexts.push_back(tc); } - for (int i=0; i < this->numThreads; i++) { - this->thread[i]->funcExeInst = 0; + this->thread[i]->setFuncExeInst(0); } // Sets CPU pointers. These must be set at this level because the CPU @@ -218,14 +246,14 @@ AlphaFullCPU<Impl>::AlphaTC::activate(int delay) #endif if (thread->status() == ThreadContext::Unallocated) { - cpu->activateWhenReady(thread->tid); + cpu->activateWhenReady(thread->readTid()); return; } thread->setStatus(ThreadContext::Active); // status() == Suspended - cpu->activateContext(thread->tid, delay); + cpu->activateContext(thread->readTid(), delay); } template <class Impl> @@ -251,7 +279,7 @@ AlphaFullCPU<Impl>::AlphaTC::suspend() #endif */ thread->setStatus(ThreadContext::Suspended); - cpu->suspendContext(thread->tid); + cpu->suspendContext(thread->readTid()); } template <class Impl> @@ -264,7 +292,7 @@ AlphaFullCPU<Impl>::AlphaTC::deallocate() return; thread->setStatus(ThreadContext::Unallocated); - cpu->deallocateContext(thread->tid); + cpu->deallocateContext(thread->readTid()); } template <class Impl> @@ -277,7 +305,7 @@ AlphaFullCPU<Impl>::AlphaTC::halt() return; thread->setStatus(ThreadContext::Halted); - cpu->haltContext(thread->tid); + cpu->haltContext(thread->readTid()); } template <class Impl> @@ -349,7 +377,7 @@ template <class Impl> TheISA::MachInst AlphaFullCPU<Impl>::AlphaTC:: getInst() { - return thread->inst; + return thread->getInst(); } template <class Impl> @@ -358,7 +386,7 @@ AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc) { // This function will mess things up unless the ROB is empty and // there are no instructions in the pipeline. - unsigned tid = thread->tid; + unsigned tid = thread->readTid(); PhysRegIndex renamed_reg; // First loop through the integer registers. @@ -400,7 +428,7 @@ template <class Impl> uint64_t AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx) { - return cpu->readArchIntReg(reg_idx, thread->tid); + return cpu->readArchIntReg(reg_idx, thread->readTid()); } template <class Impl> @@ -409,9 +437,9 @@ AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width) { switch(width) { case 32: - return cpu->readArchFloatRegSingle(reg_idx, thread->tid); + return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); case 64: - return cpu->readArchFloatRegDouble(reg_idx, thread->tid); + return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); default: panic("Unsupported width!"); return 0; @@ -422,7 +450,7 @@ template <class Impl> FloatReg AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx) { - return cpu->readArchFloatRegSingle(reg_idx, thread->tid); + return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } template <class Impl> @@ -430,25 +458,25 @@ FloatRegBits AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); - return cpu->readArchFloatRegInt(reg_idx, thread->tid); + return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } template <class Impl> FloatRegBits AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx) { - return cpu->readArchFloatRegInt(reg_idx, thread->tid); + return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val) { - cpu->setArchIntReg(reg_idx, val, thread->tid); + cpu->setArchIntReg(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -458,16 +486,16 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) { switch(width) { case 32: - cpu->setArchFloatRegSingle(reg_idx, val, thread->tid); + cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); break; case 64: - cpu->setArchFloatRegDouble(reg_idx, val, thread->tid); + cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); break; } // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -475,10 +503,10 @@ template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val) { - cpu->setArchFloatRegSingle(reg_idx, val, thread->tid); + cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -488,11 +516,11 @@ AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); - cpu->setArchFloatRegInt(reg_idx, val, thread->tid); + cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -500,11 +528,11 @@ template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) { - cpu->setArchFloatRegInt(reg_idx, val, thread->tid); + cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -512,11 +540,11 @@ template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val) { - cpu->setPC(val, thread->tid); + cpu->setPC(val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -524,11 +552,11 @@ template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val) { - cpu->setNextPC(val, thread->tid); + cpu->setNextPC(val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } } @@ -536,11 +564,11 @@ template <class Impl> Fault AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid); + Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } return ret_fault; @@ -551,11 +579,12 @@ Fault AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid); + Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, + thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->tid); + cpu->squashFromTC(thread->readTid()); } return ret_fault; @@ -567,21 +596,21 @@ template <class Impl> TheISA::IntReg AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i) { - return cpu->getSyscallArg(i, thread->tid); + return cpu->getSyscallArg(i, thread->readTid()); } template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val) { - cpu->setSyscallArg(i, val, thread->tid); + cpu->setSyscallArg(i, val, thread->readTid()); } template <class Impl> void AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value) { - cpu->setSyscallReturn(return_value, thread->tid); + cpu->setSyscallReturn(return_value, thread->readTid()); } #endif // FULL_SYSTEM @@ -749,8 +778,8 @@ AlphaFullCPU<Impl>::processInterrupts() this->setMiscReg(IPR_INTID, ipl, 0); // Checker needs to know these two registers were updated. if (this->checker) { - this->checker->cpuXCBase()->setMiscReg(IPR_ISR, summary); - this->checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl); + this->checker->threadBase()->setMiscReg(IPR_ISR, summary); + this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); } this->trap(Fault(new InterruptFault), 0); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index f523766cc..c5f78d63d 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -38,7 +38,7 @@ #include "cpu/activity.hh" #include "cpu/checker/cpu.hh" -#include "cpu/cpu_exec_context.hh" +#include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_impl.hh" @@ -245,12 +245,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params) } rename.setFreeList(&freeList); - // Setup the page table for whichever stages need it. -#if !FULL_SYSTEM -// fetch.setPageTable(pTable); -// iew.setPageTable(pTable); -#endif - // Setup the ROB for whichever stages need it. commit.setROB(&rob); @@ -427,12 +421,12 @@ FullO3CPU<Impl>::insertThread(unsigned tid) { DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); // Will change now that the PC and thread state is internal to the CPU - // and not in the CPUExecContext. + // and not in the ThreadContext. #if 0 #if FULL_SYSTEM ThreadContext *src_tc = system->threadContexts[tid]; #else - CPUExecContext *src_tc = thread[tid]; + ThreadContext *src_tc = thread[tid]; #endif //Bind Int Regs to Rename Map diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 69f52f147..8e482f1e5 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -43,7 +43,7 @@ #include "config/full_system.hh" #include "cpu/activity.hh" #include "cpu/base.hh" -#include "cpu/cpu_exec_context.hh" +#include "cpu/simple_thread.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/cpu_policy.hh" #include "cpu/o3/scoreboard.hh" @@ -237,11 +237,11 @@ class FullO3CPU : public BaseFullCPU #else /** Get instruction asid. */ int getInstAsid(unsigned tid) - { return thread[tid]->asid; } + { return thread[tid]->getInstAsid(); } /** Get data asid. */ int getDataAsid(unsigned tid) - { return thread[tid]->asid; } + { return thread[tid]->getDataAsid(); } #endif diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 7322161e6..38d37ec96 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -58,14 +58,6 @@ struct O3ThreadState : public ThreadState { typedef ThreadContext::Status Status; typedef typename Impl::FullCPU FullCPU; - /** Current status of the thread. */ - Status _status; - - /** Current instruction the thread is committing. Only set and - * used for DTB faults currently. - */ - TheISA::MachInst inst; - private: /** Pointer to the CPU. */ FullCPU *cpu; @@ -81,8 +73,8 @@ struct O3ThreadState : public ThreadState { bool trapPending; #if FULL_SYSTEM - O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem) - : ThreadState(-1, _thread_num, _mem), + O3ThreadState(FullCPU *_cpu, int _thread_num, ) + : ThreadState(-1, _thread_num), inSyscall(0), trapPending(0) { } #else @@ -99,25 +91,6 @@ struct O3ThreadState : public ThreadState { /** Returns a pointer to the TC of this thread. */ ThreadContext *getTC() { return tc; } - /** Returns the status of this thread. */ - Status status() const { return _status; } - - /** Sets the status of this thread. */ - void setStatus(Status new_status) { _status = new_status; } - - /** Sets the current instruction being committed. */ - void setInst(TheISA::MachInst _inst) { inst = _inst; } - - /** Reads the number of instructions functionally executed and - * committed. - */ - Counter readFuncExeInst() { return funcExeInst; } - - /** Sets the total number of instructions functionally executed - * and committed. - */ - void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } - #if !FULL_SYSTEM /** Handles the syscall. */ void syscall(int64_t callnum) { process->syscall(callnum, tc); } |