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-rw-r--r--src/cpu/o3/commit_impl.hh4
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index b0c8bee77..a18271918 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -975,7 +975,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Use checker prior to updating anything due to traps or PC
// based events.
if (cpu->checker) {
- cpu->checker->tick(head_inst);
+ cpu->checker->verify(head_inst);
}
// Check if the instruction caused a fault. If so, trap.
@@ -993,7 +993,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
if (cpu->checker && head_inst->isStore()) {
- cpu->checker->tick(head_inst);
+ cpu->checker->verify(head_inst);
}
assert(!thread[tid]->inSyscall);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b48d7fb74..6e201ea5f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -789,7 +789,7 @@ LSQUnit<Impl>::storePostSend(Packet *pkt)
// verify the value in memory for stores.
storeQueue[storeWBIdx].inst->setCompleted();
if (cpu->checker) {
- cpu->checker->tick(storeQueue[storeWBIdx].inst);
+ cpu->checker->verify(storeQueue[storeWBIdx].inst);
}
}
@@ -885,7 +885,7 @@ LSQUnit<Impl>::completeStore(int store_idx)
// may get reported twice to the checker, but the checker can
// handle that case.
if (cpu->checker) {
- cpu->checker->tick(storeQueue[store_idx].inst);
+ cpu->checker->verify(storeQueue[store_idx].inst);
}
}