diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 3 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 4 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 942970f5f..9eead4f49 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -106,8 +106,8 @@ class FullO3CPU : public BaseO3CPU SwitchedOut }; - TheISA::ITB * itb; - TheISA::DTB * dtb; + TheISA::TLB * itb; + TheISA::TLB * dtb; /** Overall CPU status. */ Status _status; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 79a4f2b7a..f9cc78c18 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -601,7 +601,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid memReq[tid] = mem_req; // Translate the instruction request. - fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC()); + fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(), + false, true); // In the case of faults, the fetch stage may need to stall and wait // for the ITB miss to be handled. diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index f3058925d..c402e8fd9 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -67,10 +67,10 @@ class O3ThreadContext : public ThreadContext O3ThreadState<Impl> *thread; /** Returns a pointer to the ITB. */ - TheISA::ITB *getITBPtr() { return cpu->itb; } + TheISA::TLB *getITBPtr() { return cpu->itb; } /** Returns a pointer to the DTB. */ - TheISA::DTB *getDTBPtr() { return cpu->dtb; } + TheISA::TLB *getDTBPtr() { return cpu->dtb; } /** Returns a pointer to this CPU. */ virtual BaseCPU *getCpuPtr() { return cpu; } |