4 files changed, 37 insertions, 26 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 785165636..38e6a0b5b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -557,12 +557,6 @@ template <class Impl>
 void
 FullO3CPU<Impl>::activateContext(int tid, int delay)
 {
-#if FULL_SYSTEM
-    // Connect the ThreadContext's memory ports (Functional/Virtual
-    // Ports)
-    threadContexts[tid]->connectMemPorts();
-#endif
-
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
@@ -781,6 +775,18 @@ FullO3CPU<Impl>::activateWhenReady(int tid)
     }
 }
 
+#if FULL_SYSTEM
+template <class Impl>
+void
+FullO3CPU<Impl>::updateMemPorts()
+{
+    // Update all ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    for (int i = 0; i < thread.size(); ++i)
+        thread[i]->connectMemPorts();
+}
+#endif
+
 template <class Impl>
 void
 FullO3CPU<Impl>::serialize(std::ostream &os)
@@ -941,7 +947,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     activityRec.reset();
 
-    BaseCPU::takeOverFrom(oldCPU);
+    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
 
     fetch.takeOverFrom();
     decode.takeOverFrom();
@@ -978,25 +984,6 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
     }
     if (!tickEvent.scheduled())
         tickEvent.schedule(curTick);
-
-    Port *peer;
-    Port *icachePort = fetch.getIcachePort();
-    if (icachePort->getPeer() == NULL) {
-        peer = oldCPU->getPort("icache_port")->getPeer();
-        icachePort->setPeer(peer);
-    } else {
-        peer = icachePort->getPeer();
-    }
-    peer->setPeer(icachePort);
-
-    Port *dcachePort = iew.getDcachePort();
-    if (dcachePort->getPeer() == NULL) {
-        peer = oldCPU->getPort("dcache_port")->getPeer();
-        dcachePort->setPeer(peer);
-    } else {
-        peer = dcachePort->getPeer();
-    }
-    peer->setPeer(dcachePort);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d217a3e85..ea374dd57 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -357,6 +357,10 @@ class FullO3CPU : public BaseO3CPU
     { return globalSeqNum++; }
 
 #if FULL_SYSTEM
+    /** Update the Virt and Phys ports of all ThreadContexts to
+     * reflect change in memory connections. */
+    void updateMemPorts();
+
     /** Check if this address is a valid instruction address. */
     bool validInstAddr(Addr addr) { return true; }
 
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index e68085cfd..80f53a726 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -300,6 +300,8 @@ class LSQ {
 
         bool snoopRangeSent;
 
+        virtual void setPeer(Port *port);
+
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -327,6 +329,11 @@ class LSQ {
     /** D-cache port. */
     DcachePort dcachePort;
 
+#if FULL_SYSTEM
+    /** Tell the CPU to update the Phys and Virt ports. */
+    void updateMemPorts() { cpu->updateMemPorts(); }
+#endif
+
   protected:
     /** The LSQ policy for SMT mode. */
     LSQPolicy lsqPolicy;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index fb738f7c9..d4994fcb7 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -34,6 +34,19 @@
 
 #include "cpu/o3/lsq.hh"
 
+template<class Impl>
+void
+LSQ<Impl>::DcachePort::setPeer(Port *port)
+{
+    Port::setPeer(port);
+
+#if FULL_SYSTEM
+    // Update the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    lsq->updateMemPorts();
+#endif
+}
+
 template <class Impl>
 Tick
 LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)