3 files changed, 12 insertions, 0 deletions

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 0a6d309fe..a30bf7f5f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1182,8 +1182,12 @@ InstructionQueue<Impl>::getDeferredMemInstToExecute()
         // 2. virtual fence ahead
         // 3. not ready to expose and gets a TLB miss
         // for both (2, 3) we need to restart the translation
+
+      DPRINTF(IQ, "sn:%lli onlyWaitForFence = %d, fenceDelay = %d\n", (*it)->seqNum, (*it)->onlyWaitForFence(), (*it)->fenceDelay() );
+
         if ( (*it)->translationCompleted() 
                 || ((*it)->onlyWaitForFence() && !(*it)->fenceDelay())
+                || ((*it)->onlyWaitForExpose() && (*it)->readyToExpose())
                 || (*it)->isSquashed()) {
             DynInstPtr mem_inst = std::move(*it);
             mem_inst->onlyWaitForFence(false);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ebc963d5b..80445e261 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -128,6 +128,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         DPRINTF(LSQUnit, "spec load miss for inst [sn:%lli], fence it.\n",
                 inst->seqNum);
         inst->fenceDelay(true);
+    } else {
+        DPRINTF(LSQUnit, "spec load hit for inst [sn:%lli].\n");
     }
 
     assert(!cpu->switchedOut());
@@ -918,6 +920,7 @@ LSQUnit<Impl>::updateVisibleState()
     //iterate all the loads and update its fencedelay state accordingly
     while (load_idx != loadTail && loadQueue[load_idx]){
         DynInstPtr inst = loadQueue[load_idx];
+        DPRINTF(LSQUnit, "update visible state for inst [sn:%lli].\n", inst->seqNum);
 
         if (!loadInExec){
 
@@ -981,6 +984,7 @@ LSQUnit<Impl>::updateVisibleState()
                     assert(0);
                     //--loadsToVLD;
                   }
+                  DPRINTF(LSQUnit, "inst [sn:%lli] not ready to expose.\n", inst->seqNum);
                   inst->readyToExpose(false);
                 } else {
                   /* set taint for dst registers */
@@ -1370,7 +1374,10 @@ LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
 
     if (inst->fenceDelay()) {
         DPRINTF(LSQUnit, "To write back a fence delayed spec load [sn:%lli].\n", inst->seqNum);
+        assert(pkt->isSpec());
         inst->onlyWaitForFence(true);
+        inst->translationStarted(false);
+        inst->translationCompleted(false);
         iewStage->instQueue.deferMemInst(inst);
     } else if (!inst->isExecuted()) {
         inst->setExecuted();
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index b729a9d00..32cfe04a1 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -434,6 +434,7 @@ ROB<Impl>::updateVisibleState()
 
         while (inst_it != tail_inst_it) {
             DynInstPtr inst = *inst_it++;
+            DPRINTF(ROB, "updating rob visible state for [sn:%lli]\n", inst->seqNum);
 
             assert(inst!=0);