diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 9 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.hh | 3 |
2 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 78fbd6694..54c55f8c7 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -258,10 +258,9 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) globalSeqNum(1), system(params->system), drainCount(0), - deferRegistration(params->defer_registration), lastRunningCycle(curCycle()) { - if (!deferRegistration) { + if (!params->switched_out) { _status = Running; } else { _status = SwitchedOut; @@ -461,7 +460,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) } // FullO3CPU always requires an interrupt controller. - if (!params->defer_registration && !interrupts) { + if (!params->switched_out && !interrupts) { fatal("FullO3CPU %s has no interrupt controller.\n" "Ensure createInterruptController() is called.\n", name()); } @@ -647,7 +646,7 @@ FullO3CPU<Impl>::init() { BaseCPU::init(); - if (!params()->defer_registration && + if (!params()->switched_out && system->getMemoryMode() != Enums::timing) { fatal("The O3 CPU requires the memory system to be in " "'timing' mode.\n"); @@ -668,7 +667,7 @@ FullO3CPU<Impl>::init() if (icachePort.isConnected()) fetch.setIcache(); - if (FullSystem && !params()->defer_registration) { + if (FullSystem && !params()->switched_out) { for (ThreadID tid = 0; tid < numThreads; tid++) { ThreadContext *src_tc = threadContexts[tid]; TheISA::initCPU(src_tc, src_tc->contextId()); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index eda9d9e91..c6083d8d5 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -741,9 +741,6 @@ class FullO3CPU : public BaseO3CPU /** Pointers to all of the threads in the CPU. */ std::vector<Thread *> thread; - /** Whether or not the CPU should defer its registration. */ - bool deferRegistration; - /** Is there a context switch pending? */ bool contextSwitch; |