summaryrefslogtreecommitdiff
path: root/src/cpu/o3
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/cpu.cc15
-rw-r--r--src/cpu/o3/cpu.hh8
-rw-r--r--src/cpu/o3/fetch_impl.hh4
-rw-r--r--src/cpu/o3/lsq.hh4
-rw-r--r--src/cpu/o3/lsq_impl.hh11
-rw-r--r--src/cpu/o3/lsq_unit.hh4
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh4
7 files changed, 21 insertions, 29 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fe70c3fcf..e8fc968b7 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -87,9 +87,8 @@ BaseO3CPU::regStats()
template<class Impl>
bool
-FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
+FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
DPRINTF(O3CPU, "Fetch unit received timing\n");
// We shouldn't ever get a block in ownership state
assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
@@ -107,18 +106,16 @@ FullO3CPU<Impl>::IcachePort::recvRetry()
template <class Impl>
bool
-FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
+FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
- return lsq->recvTiming(pkt);
+ return lsq->recvTimingResp(pkt);
}
template <class Impl>
-bool
-FullO3CPU<Impl>::DcachePort::recvTimingSnoop(PacketPtr pkt)
+void
+FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
{
- assert(pkt->isRequest());
- return lsq->recvTimingSnoop(pkt);
+ lsq->recvTimingSnoopReq(pkt);
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index be51f415f..41128110b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -148,8 +148,8 @@ class FullO3CPU : public BaseO3CPU
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
- virtual bool recvTiming(PacketPtr pkt);
- virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt) { }
/** Handles doing a retry of a failed fetch. */
virtual void recvRetry();
@@ -176,8 +176,8 @@ class FullO3CPU : public BaseO3CPU
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
* memory. */
- virtual bool recvTiming(PacketPtr pkt);
- virtual bool recvTimingSnoop(PacketPtr pkt);
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
/** Handles doing a retry of the previous send. */
virtual void recvRetry();
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 2480211e4..f4ce77f22 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -621,7 +621,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
fetchedCacheLines++;
// Access the cache.
- if (!cpu->getInstPort().sendTiming(data_pkt)) {
+ if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
assert(retryPkt == NULL);
assert(retryTid == InvalidThreadID);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
@@ -1356,7 +1356,7 @@ DefaultFetch<Impl>::recvRetry()
assert(retryTid != InvalidThreadID);
assert(fetchStatus[retryTid] == IcacheWaitRetry);
- if (cpu->getInstPort().sendTiming(retryPkt)) {
+ if (cpu->getInstPort().sendTimingReq(retryPkt)) {
fetchStatus[retryTid] = IcacheWaitResponse;
retryPkt = NULL;
retryTid = InvalidThreadID;
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index dac5fab18..026033539 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -297,9 +297,9 @@ class LSQ {
*
* @param pkt Response packet from the memory sub-system
*/
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
- bool recvTimingSnoop(PacketPtr pkt);
+ void recvTimingSnoopReq(PacketPtr pkt);
/** The CPU pointer. */
O3CPU *cpu;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index c2f410e37..72ffdd58b 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -319,9 +319,8 @@ LSQ<Impl>::recvRetry()
template <class Impl>
bool
-LSQ<Impl>::recvTiming(PacketPtr pkt)
+LSQ<Impl>::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
if (pkt->isError())
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
@@ -330,10 +329,9 @@ LSQ<Impl>::recvTiming(PacketPtr pkt)
}
template <class Impl>
-bool
-LSQ<Impl>::recvTimingSnoop(PacketPtr pkt)
+void
+LSQ<Impl>::recvTimingSnoopReq(PacketPtr pkt)
{
- assert(pkt->isRequest());
DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
pkt->cmdString());
@@ -345,9 +343,6 @@ LSQ<Impl>::recvTimingSnoop(PacketPtr pkt)
thread[tid].checkSnoop(pkt);
}
}
-
- // to provide stronger consistency model
- return true;
}
template<class Impl>
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 44c3df0bf..ad1e26d2f 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -801,7 +801,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
state->mainPkt = data_pkt;
}
- if (!dcachePort->sendTiming(fst_data_pkt)) {
+ if (!dcachePort->sendTimingReq(fst_data_pkt)) {
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
@@ -830,7 +830,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
// The first packet will return in completeDataAccess and be
// handled there.
++usedPorts;
- if (!dcachePort->sendTiming(snd_data_pkt)) {
+ if (!dcachePort->sendTimingReq(snd_data_pkt)) {
// The main packet will be deleted in completeDataAccess.
delete snd_data_pkt->req;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f4182e30d..4f82ad9e3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1180,7 +1180,7 @@ template <class Impl>
bool
LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
{
- if (!dcachePort->sendTiming(data_pkt)) {
+ if (!dcachePort->sendTimingReq(data_pkt)) {
// Need to handle becoming blocked on a store.
isStoreBlocked = true;
++lsqCacheBlocked;
@@ -1203,7 +1203,7 @@ LSQUnit<Impl>::recvRetry()
LSQSenderState *state =
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
- if (dcachePort->sendTiming(retryPkt)) {
+ if (dcachePort->sendTimingReq(retryPkt)) {
// Don't finish the store unless this is the last packet.
if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
state->pendingPacket == retryPkt) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 03:20:38 +0000