diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 8 | ||||
| -rw-r--r-- | src/cpu/o3/sparc/dyn_inst.hh | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 6c27e890a..20759d849 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -125,7 +125,7 @@ class AlphaDynInst : public BaseDynInst<Impl> } /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) { return this->cpu->readMiscRegNoEffect( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, @@ -135,7 +135,7 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) { return this->cpu->readMiscReg( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, @@ -143,7 +143,7 @@ class AlphaDynInst : public BaseDynInst<Impl> } /** Sets a misc. register. */ - void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val) + void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) { this->instResult.integer = val; return this->cpu->setMiscRegNoEffect( @@ -154,7 +154,7 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegOperandWithEffect(const StaticInst *si, int idx, + void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) { return this->cpu->setMiscReg( diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh index bd61b0384..72242b161 100644 --- a/src/cpu/o3/sparc/dyn_inst.hh +++ b/src/cpu/o3/sparc/dyn_inst.hh @@ -107,7 +107,7 @@ class SparcDynInst : public BaseDynInst<Impl> } /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) { return this->cpu->readMiscRegNoEffect( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, @@ -117,7 +117,7 @@ class SparcDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) { return this->cpu->readMiscReg( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, @@ -125,7 +125,7 @@ class SparcDynInst : public BaseDynInst<Impl> } /** Sets a misc. register. */ - void setMiscRegOperand(const StaticInst * si, + void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const TheISA::MiscReg &val) { this->instResult.integer = val; @@ -137,7 +137,7 @@ class SparcDynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegOperandWithEffect( + void setMiscRegOperand( const StaticInst *si, int idx, const TheISA::MiscReg &val) { return this->cpu->setMiscReg( |