10 files changed, 16 insertions, 82 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 01749a2a2..b62550062 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     void post_interrupt(int int_num, int index);
     /** HW return from error interrupt. */
     Fault hwrei(unsigned tid);
-    /** Returns if a specific PC is a PAL mode PC. */
-    bool inPalMode(uint64_t PC)
-    { return AlphaISA::PcPAL(PC); }
 
     bool simPalCheck(int palFunc, unsigned tid);
 
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index f5c2170ce..04eadfa5a 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -48,8 +48,8 @@
 #if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
 #include "cpu/quiesce_event.hh"
-#include "kern/kernel_stats.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
 #endif
@@ -270,7 +270,6 @@ template <class Impl>
 void
 AlphaO3CPU<Impl>::processInterrupts()
 {
-    using namespace TheISA;
     // Check for interrupts here.  For now can copy the code that
     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
     // is the one that handles the interrupts.
@@ -279,51 +278,11 @@ AlphaO3CPU<Impl>::processInterrupts()
 
     // Check if there are any outstanding interrupts
     //Handle the interrupts
-    int ipl = 0;
-    int summary = 0;
-
-    this->checkInterrupts = false;
-
-    if (this->readMiscReg(IPR_ASTRR, 0))
-        panic("asynchronous traps not implemented\n");
-
-    if (this->readMiscReg(IPR_SIRR, 0)) {
-        for (int i = INTLEVEL_SOFTWARE_MIN;
-             i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    uint64_t interrupts = this->intr_status();
+    Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
 
-    if (interrupts) {
-        for (int i = INTLEVEL_EXTERNAL_MIN;
-             i < INTLEVEL_EXTERNAL_MAX; i++) {
-            if (interrupts & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = i;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) {
-        this->setMiscReg(IPR_ISR, summary, 0);
-        this->setMiscReg(IPR_INTID, ipl, 0);
-        // Checker needs to know these two registers were updated.
-#if USE_CHECKER
-        if (this->checker) {
-            this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
-            this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
-        }
-#endif
-        this->trap(Fault(new InterruptFault), 0);
-        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                this->readMiscReg(IPR_IPLR, 0), ipl, summary);
+    if (interrupt != NoFault) {
+        this->checkInterrupts = false;
+        this->trap(interrupt, 0);
     }
 }
 
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index e711de510..31df8ff78 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
 #if FULL_SYSTEM
     /** Calls hardware return from error interrupt. */
     Fault hwrei();
-    /** Checks if system is in PAL mode. */
-    bool inPalMode();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index f27cd5961..6fc548a85 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -113,7 +113,7 @@ Fault
 AlphaDynInst<Impl>::hwrei()
 {
     // Can only do a hwrei when in pal mode.
-    if (!this->cpu->inPalMode(this->readPC()))
+    if (!(this->readPC() & 0x3))
         return new AlphaISA::UnimplementedOpcodeFault;
 
     // Set the next PC based on the value of the EXC_ADDR IPR.
@@ -128,13 +128,6 @@ AlphaDynInst<Impl>::hwrei()
 }
 
 template <class Impl>
-bool
-AlphaDynInst<Impl>::inPalMode()
-{
-    return this->cpu->inPalMode(this->PC);
-}
-
-template <class Impl>
 void
 AlphaDynInst<Impl>::trap(Fault fault)
 {
diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index f0cecee35..bcecb7087 100644
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext<Impl>
     {
         return this->thread->quiesceEvent;
     }
-
-    /** Returns if the thread is currently in PAL mode, based on
-     * the PC's value. */
-    virtual bool inPalMode()
-    { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); }
 #endif
 
     virtual uint64_t readNextNPC()
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ecf6ed632..30052a148 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -35,6 +35,7 @@
 #include <algorithm>
 #include <string>
 
+#include "arch/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/timebuf.hh"
 #include "cpu/exetrace.hh"
@@ -638,8 +639,7 @@ DefaultCommit<Impl>::commit()
     // and no other traps or external squashes are currently pending.
     // @todo: Allow other threads to handle interrupts.
     if (cpu->checkInterrupts &&
-        cpu->check_interrupts() &&
-        !cpu->inPalMode(readPC()) &&
+        cpu->check_interrupts(cpu->tcBase(0)) &&
         !trapSquash[0] &&
         !tcSquash[0]) {
         // Tell fetch that there is an interrupt pending.  This will
@@ -1085,8 +1085,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
 #if FULL_SYSTEM
     if (thread[tid]->profile) {
-//        bool usermode =
-//            (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
+//        bool usermode = TheISA::inUserMode(thread[tid]->getTC());
 //        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
         thread[tid]->profilePC = head_inst->readPC();
         ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 31f3b96d6..5ef6e27ea 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -45,7 +45,6 @@
 #if FULL_SYSTEM
 #include "arch/tlb.hh"
 #include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
 #include "sim/system.hh"
 #endif // FULL_SYSTEM
 
@@ -559,14 +558,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
 {
     Fault fault = NoFault;
 
-#if FULL_SYSTEM
-    // Flag to say whether or not address is physical addr.
-    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
-#else
-    unsigned flags = 0;
-#endif // FULL_SYSTEM
-
-    if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
+    //AlphaDep
+    if (cacheBlocked || isSwitchedOut() ||
+            (interruptPending && (fetch_PC & 0x3))) {
         // Hold off fetch from getting new instructions when:
         // Cache is blocked, or
         // while an interrupt is pending and we're not in PAL mode, or
@@ -585,7 +579,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     // Setup the memReq to do a read of the first instruction's address.
     // Set the appropriate read size and flags as well.
     // Build request here.
-    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
+    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
                                      fetch_PC, cpu->readCpuId(), tid);
 
     memReq[tid] = mem_req;
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 29ee19e49..598af123e 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -39,8 +39,7 @@
 #include "cpu/o3/comm.hh"
 
 #if FULL_SYSTEM
-#include "kern/kernel_stats.hh"
-
+#include "arch/kernel_stats.hh"
 #endif
 
 #include <vector>
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 4556c5e22..daee2fc7d 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -83,7 +83,7 @@ class O3ThreadContext : public ThreadContext
     virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
 
     /** Returns a pointer to this thread's kernel statistics. */
-    virtual Kernel::Statistics *getKernelStats()
+    virtual TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
 
     virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 81750ada7..8d623f5b8 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -194,7 +194,7 @@ void
 O3ThreadContext<Impl>::regStats(const std::string &name)
 {
 #if FULL_SYSTEM
-    thread->kernelStats = new Kernel::Statistics(cpu->system);
+    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
     thread->kernelStats->regStats(name + ".kern");
 #endif
 }