5 files changed, 8 insertions, 23 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 82f17adc9..7f24ee988 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -578,18 +578,6 @@ FullO3CPU<Impl>::regStats()
 }
 
 template <class Impl>
-Port *
-FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
-{
-    if (if_name == "dcache_port")
-        return &dcachePort;
-    else if (if_name == "icache_port")
-        return &icachePort;
-    else
-        panic("No Such Port\n");
-}
-
-template <class Impl>
 void
 FullO3CPU<Impl>::tick()
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1c713097a..f48c0f0f2 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -361,9 +361,6 @@ class FullO3CPU : public BaseO3CPU
         this->dtb->demapPage(vaddr, asn);
     }
 
-    /** Returns a specific port. */
-    Port *getPort(const std::string &if_name, int idx);
-
     /** Ticks CPU, calling tick() on each stage, and checking the overall
      *  activity to see if the CPU should deschedule itself.
      */
@@ -781,10 +778,10 @@ class FullO3CPU : public BaseO3CPU
     }
 
     /** Used by the fetch unit to get a hold of the instruction port. */
-    Port* getIcachePort() { return &icachePort; }
+    virtual CpuPort &getInstPort() { return icachePort; }
 
     /** Get the dcache port (used to find block size for translations). */
-    Port* getDcachePort() { return &dcachePort; }
+    virtual CpuPort &getDataPort() { return dcachePort; }
 
     Addr lockAddr;
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3dca6e8ba..1271ea481 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -335,10 +335,10 @@ template<class Impl>
 void
 DefaultFetch<Impl>::setIcache()
 {
-    assert(cpu->getIcachePort()->isConnected());
+    assert(cpu->getInstPort().isConnected());
 
     // Size of cache block.
-    cacheBlkSize = cpu->getIcachePort()->peerBlockSize();
+    cacheBlkSize = cpu->getInstPort().peerBlockSize();
 
     // Create mask to get rid of offset bits.
     cacheBlkMask = (cacheBlkSize - 1);
@@ -623,7 +623,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
         fetchedCacheLines++;
 
         // Access the cache.
-        if (!cpu->getIcachePort()->sendTiming(data_pkt)) {
+        if (!cpu->getInstPort().sendTiming(data_pkt)) {
             assert(retryPkt == NULL);
             assert(retryTid == InvalidThreadID);
             DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
@@ -1358,7 +1358,7 @@ DefaultFetch<Impl>::recvRetry()
         assert(retryTid != InvalidThreadID);
         assert(fetchStatus[retryTid] == IcacheWaitRetry);
 
-        if (cpu->getIcachePort()->sendTiming(retryPkt)) {
+        if (cpu->getInstPort().sendTiming(retryPkt)) {
             fetchStatus[retryTid] = IcacheWaitResponse;
             retryPkt = NULL;
             retryTid = InvalidThreadID;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 97b41ad9f..209ad317b 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -302,7 +302,7 @@ DefaultIEW<Impl>::initStage()
 // Initialize the checker's dcache port here
 #if USE_CHECKER
     if (cpu->checker) {
-        cpu->checker->setDcachePort(cpu->getDcachePort());
+        cpu->checker->setDcachePort(&cpu->getDataPort());
      }
 #endif
 
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index f1642be9c..02758f212 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -111,7 +111,7 @@ LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         thread[tid].init(cpu, iew_ptr, params, this,
                          maxLQEntries, maxSQEntries, tid);
-        thread[tid].setDcachePort(cpu_ptr->getDcachePort());
+        thread[tid].setDcachePort(&cpu_ptr->getDataPort());
     }
 }