diff options
Diffstat (limited to 'src/cpu/o3')
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 1 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 88cf75f4f..27f8e9561 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext virtual int flattenIntIndex(int reg); virtual int flattenFloatIndex(int reg); virtual int flattenCCIndex(int reg); + virtual int flattenMiscIndex(int reg); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index c818260f4..43e903135 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -292,6 +292,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg) } template <class Impl> +int +O3ThreadContext<Impl>::flattenMiscIndex(int reg) +{ + return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { |