diff options
Diffstat (limited to 'src/cpu/o3')
68 files changed, 1098 insertions, 4490 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index f0284b2cf..56e537ad2 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -38,10 +38,7 @@ if build_env['USE_CHECKER']: class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' activity = Param.Unsigned(0, "Initial count") - numThreads = Param.Unsigned(1, "number of HW thread contexts") - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") if build_env['USE_CHECKER']: if not build_env['FULL_SYSTEM']: checker = Param.BaseCPU(O3Checker(workload=Parent.workload, @@ -134,9 +131,6 @@ class DerivO3CPU(BaseCPU): instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") - smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py index 43a71d67b..edc6dc9b6 100644 --- a/src/cpu/o3/O3Checker.py +++ b/src/cpu/o3/O3Checker.py @@ -39,5 +39,3 @@ class O3Checker(BaseCPU): "If a load result is incorrect, only print a warning and do not exit") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index 2de106d8b..f05986bf5 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -51,7 +51,9 @@ if 'O3CPU' in env['CPU_MODELS']: Source('bpred_unit.cc') Source('commit.cc') Source('cpu.cc') + Source('cpu_builder.cc') Source('decode.cc') + Source('dyn_inst.cc') Source('fetch.cc') Source('free_list.cc') Source('fu_pool.cc') @@ -65,6 +67,7 @@ if 'O3CPU' in env['CPU_MODELS']: Source('rob.cc') Source('scoreboard.cc') Source('store_set.cc') + Source('thread_context.cc') TraceFlag('FreeList') TraceFlag('LSQ') @@ -81,24 +84,6 @@ if 'O3CPU' in env['CPU_MODELS']: 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) - if env['TARGET_ISA'] == 'alpha': - Source('alpha/cpu.cc') - Source('alpha/cpu_builder.cc') - Source('alpha/dyn_inst.cc') - Source('alpha/thread_context.cc') - elif env['TARGET_ISA'] == 'mips': - Source('mips/cpu.cc') - Source('mips/cpu_builder.cc') - Source('mips/dyn_inst.cc') - Source('mips/thread_context.cc') - elif env['TARGET_ISA'] == 'sparc': - Source('sparc/cpu.cc') - Source('sparc/cpu_builder.cc') - Source('sparc/dyn_inst.cc') - Source('sparc/thread_context.cc') - else: - sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) - if env['USE_CHECKER']: SimObject('O3Checker.py') Source('checker_builder.cc') diff --git a/src/cpu/o3/alpha/cpu.cc b/src/cpu/o3/alpha/cpu.cc deleted file mode 100644 index ed10b2fd1..000000000 --- a/src/cpu/o3/alpha/cpu.cc +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include "cpu/o3/alpha/impl.hh" -#include "cpu/o3/alpha/cpu_impl.hh" -#include "cpu/o3/alpha/dyn_inst.hh" - -// Force instantiation of AlphaO3CPU for all the implemntations that are -// needed. Consider merging this and alpha_dyn_inst.cc, and maybe all -// classes that depend on a certain impl, into one file (alpha_impl.cc?). -template class AlphaO3CPU<AlphaSimpleImpl>; diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh deleted file mode 100644 index ebc4e7b23..000000000 --- a/src/cpu/o3/alpha/cpu.hh +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_ALPHA_CPU_HH__ -#define __CPU_O3_ALPHA_CPU_HH__ - -#include "arch/regfile.hh" -#include "arch/types.hh" -#include "cpu/thread_context.hh" -#include "cpu/o3/cpu.hh" -#include "sim/byteswap.hh" - -class EndQuiesceEvent; -namespace Kernel { - class Statistics; -}; - -class TranslatingPort; - -/** - * AlphaO3CPU class. Derives from the FullO3CPU class, and - * implements all ISA and implementation specific functions of the - * CPU. This is the CPU class that is used for the SimObjects, and is - * what is given to the DynInsts. Most of its state exists in the - * FullO3CPU; the state is has is mainly for ISA specific - * functionality. - */ -template <class Impl> -class AlphaO3CPU : public FullO3CPU<Impl> -{ - public: - typedef O3ThreadState<Impl> ImplState; - typedef O3ThreadState<Impl> Thread; - typedef typename Impl::Params Params; - - /** Constructs an AlphaO3CPU with the given parameters. */ - AlphaO3CPU(Params *params); - - /** Registers statistics. */ - void regStats(); - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); - - /** Reads a misc. register, including any side effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); - - /** Sets a miscellaneous register. */ - void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, - unsigned tid); - - /** Sets a misc. register, including any side effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, - unsigned tid); - - /** Initiates a squash of all in-flight instructions for a given - * thread. The source of the squash is an external update of - * state through the TC. - */ - void squashFromTC(unsigned tid); - -#if FULL_SYSTEM - /** Posts an interrupt. */ - void post_interrupt(int int_num, int index); - /** HW return from error interrupt. */ - Fault hwrei(unsigned tid); - - bool simPalCheck(int palFunc, unsigned tid); - - /** Returns the Fault for any valid interrupt. */ - Fault getInterrupts(); - - /** Processes any an interrupt fault. */ - void processInterrupts(Fault interrupt); - - /** Halts the CPU. */ - void halt() { panic("Halt not implemented!\n"); } -#endif - - /** Traps to handle given fault. */ - void trap(Fault fault, unsigned tid); - -#if !FULL_SYSTEM - /** Executes a syscall. - * @todo: Determine if this needs to be virtual. - */ - void syscall(int64_t callnum, int tid); - /** Gets a syscall argument. */ - TheISA::IntReg getSyscallArg(int i, int tid); - - /** Used to shift args for indirect syscall. */ - void setSyscallArg(int i, TheISA::IntReg val, int tid); - - /** Sets the return value of a syscall. */ - void setSyscallReturn(SyscallReturn return_value, int tid); -#endif - - /** CPU read function, forwards read to LSQ. */ - template <class T> - Fault read(RequestPtr &req, T &data, int load_idx) - { - return this->iew.ldstQueue.read(req, data, load_idx); - } - - /** CPU write function, forwards write to LSQ. */ - template <class T> - Fault write(RequestPtr &req, T &data, int store_idx) - { - return this->iew.ldstQueue.write(req, data, store_idx); - } - - Addr lockAddr; - - /** Temporary fix for the lock flag, works in the UP case. */ - bool lockFlag; -}; - -#endif // __CPU_O3_ALPHA_CPU_HH__ diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc deleted file mode 100644 index f569c048b..000000000 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include <string> - -#include "config/use_checker.hh" -#include "cpu/base.hh" -#include "cpu/o3/alpha/cpu.hh" -#include "cpu/o3/alpha/impl.hh" -#include "cpu/o3/alpha/params.hh" -#include "cpu/o3/fu_pool.hh" -#include "params/DerivO3CPU.hh" - -class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl> -{ - public: - DerivO3CPU(AlphaSimpleParams *p) - : AlphaO3CPU<AlphaSimpleImpl>(p) - { } -}; - -DerivO3CPU * -DerivO3CPUParams::create() -{ - DerivO3CPU *cpu; - -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - int actual_num_threads = 1; -#else - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - int actual_num_threads = - (numThreads >= workload.size()) ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); - } -#endif - - AlphaSimpleParams *params = new AlphaSimpleParams; - - params->clock = clock; - params->phase = phase; - - params->tracer = tracer; - - params->name = name; - params->numberOfThreads = actual_num_threads; - params->cpu_id = cpu_id; - params->activity = activity; - - params->itb = itb; - params->dtb = dtb; - - params->system = system; -#if FULL_SYSTEM - params->profile = profile; - - params->do_quiesce = do_quiesce; - params->do_checkpoint_insts = do_checkpoint_insts; - params->do_statistics_insts = do_statistics_insts; -#else - params->workload = workload; -#endif // FULL_SYSTEM - -#if USE_CHECKER - params->checker = checker; -#endif - - params->max_insts_any_thread = max_insts_any_thread; - params->max_insts_all_threads = max_insts_all_threads; - params->max_loads_any_thread = max_loads_any_thread; - params->max_loads_all_threads = max_loads_all_threads; - params->progress_interval = progress_interval; - - // - // Caches - // - params->cachePorts = cachePorts; - - params->decodeToFetchDelay = decodeToFetchDelay; - params->renameToFetchDelay = renameToFetchDelay; - params->iewToFetchDelay = iewToFetchDelay; - params->commitToFetchDelay = commitToFetchDelay; - params->fetchWidth = fetchWidth; - - params->renameToDecodeDelay = renameToDecodeDelay; - params->iewToDecodeDelay = iewToDecodeDelay; - params->commitToDecodeDelay = commitToDecodeDelay; - params->fetchToDecodeDelay = fetchToDecodeDelay; - params->decodeWidth = decodeWidth; - - params->iewToRenameDelay = iewToRenameDelay; - params->commitToRenameDelay = commitToRenameDelay; - params->decodeToRenameDelay = decodeToRenameDelay; - params->renameWidth = renameWidth; - - params->commitToIEWDelay = commitToIEWDelay; - params->renameToIEWDelay = renameToIEWDelay; - params->issueToExecuteDelay = issueToExecuteDelay; - params->dispatchWidth = dispatchWidth; - params->issueWidth = issueWidth; - params->wbWidth = wbWidth; - params->wbDepth = wbDepth; - params->fuPool = fuPool; - - params->iewToCommitDelay = iewToCommitDelay; - params->renameToROBDelay = renameToROBDelay; - params->commitWidth = commitWidth; - params->squashWidth = squashWidth; - params->trapLatency = trapLatency; - - params->backComSize = backComSize; - params->forwardComSize = forwardComSize; - - params->predType = predType; - params->localPredictorSize = localPredictorSize; - params->localCtrBits = localCtrBits; - params->localHistoryTableSize = localHistoryTableSize; - params->localHistoryBits = localHistoryBits; - params->globalPredictorSize = globalPredictorSize; - params->globalCtrBits = globalCtrBits; - params->globalHistoryBits = globalHistoryBits; - params->choicePredictorSize = choicePredictorSize; - params->choiceCtrBits = choiceCtrBits; - - params->BTBEntries = BTBEntries; - params->BTBTagSize = BTBTagSize; - - params->RASSize = RASSize; - - params->LQEntries = LQEntries; - params->SQEntries = SQEntries; - - params->SSITSize = SSITSize; - params->LFSTSize = LFSTSize; - - params->numPhysIntRegs = numPhysIntRegs; - params->numPhysFloatRegs = numPhysFloatRegs; - params->numIQEntries = numIQEntries; - params->numROBEntries = numROBEntries; - - params->smtNumFetchingThreads = smtNumFetchingThreads; - - // Default smtFetchPolicy to "RoundRobin", if necessary. - std::string round_robin_policy = "RoundRobin"; - std::string single_thread = "SingleThread"; - - if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0) - params->smtFetchPolicy = round_robin_policy; - else - params->smtFetchPolicy = smtFetchPolicy; - - params->smtIQPolicy = smtIQPolicy; - params->smtLSQPolicy = smtLSQPolicy; - params->smtLSQThreshold = smtLSQThreshold; - params->smtROBPolicy = smtROBPolicy; - params->smtROBThreshold = smtROBThreshold; - params->smtCommitPolicy = smtCommitPolicy; - - params->instShiftAmt = 2; - - params->deferRegistration = defer_registration; - - params->functionTrace = function_trace; - params->functionTraceStart = function_trace_start; - - cpu = new DerivO3CPU(params); - - return cpu; -} diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh deleted file mode 100644 index 7f8f0547b..000000000 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include "config/use_checker.hh" - -#include "arch/alpha/faults.hh" -#include "arch/alpha/isa_traits.hh" -#include "base/cprintf.hh" -#include "base/statistics.hh" -#include "base/timebuf.hh" -#include "cpu/checker/thread_context.hh" -#include "sim/sim_events.hh" -#include "sim/stats.hh" - -#include "cpu/o3/alpha/cpu.hh" -#include "cpu/o3/alpha/params.hh" -#include "cpu/o3/alpha/thread_context.hh" -#include "cpu/o3/comm.hh" -#include "cpu/o3/thread_state.hh" - -#if FULL_SYSTEM -#include "arch/alpha/osfpal.hh" -#include "arch/isa_traits.hh" -#include "arch/kernel_stats.hh" -#include "cpu/quiesce_event.hh" -#include "sim/sim_exit.hh" -#include "sim/system.hh" -#endif - -template <class Impl> -AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(this, params) -{ - DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n"); - - // Setup any thread state. - this->thread.resize(this->numThreads); - - for (int i = 0; i < this->numThreads; ++i) { -#if FULL_SYSTEM - // SMT is not supported in FS mode yet. - assert(this->numThreads == 1); - this->thread[i] = new Thread(this, 0); - this->thread[i]->setStatus(ThreadContext::Suspended); -#else - if (i < params->workload.size()) { - DPRINTF(O3CPU, "Workload[%i] process is %#x", - i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], i); - - this->thread[i]->setStatus(ThreadContext::Suspended); - - //usedTids[i] = true; - //threadMap[i] = i; - } else { - //Allocate Empty thread so M5 can use later - //when scheduling threads to CPU - Process* dummy_proc = NULL; - - this->thread[i] = new Thread(this, i, dummy_proc, i); - //usedTids[i] = false; - } -#endif // !FULL_SYSTEM - - ThreadContext *tc; - - // Setup the TC that will serve as the interface to the threads/CPU. - AlphaTC<Impl> *alpha_tc = - new AlphaTC<Impl>; - - tc = alpha_tc; - - // If we're using a checker, then the TC should be the - // CheckerThreadContext. -#if USE_CHECKER - if (params->checker) { - tc = new CheckerThreadContext<AlphaTC<Impl> >( - alpha_tc, this->checker); - } -#endif - - alpha_tc->cpu = this; - alpha_tc->thread = this->thread[i]; - -#if FULL_SYSTEM - // Setup quiesce event. - this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); -#endif - // Give the thread the TC. - this->thread[i]->tc = tc; - this->thread[i]->setCpuId(params->cpu_id); - - // Add the TC to the CPU's list of TC's. - this->threadContexts.push_back(tc); - } - - for (int i=0; i < this->numThreads; i++) { - this->thread[i]->setFuncExeInst(0); - } - - lockAddr = 0; - lockFlag = false; -} - -template <class Impl> -void -AlphaO3CPU<Impl>::regStats() -{ - // Register stats for everything that has stats. - this->fullCPURegStats(); - this->fetch.regStats(); - this->decode.regStats(); - this->rename.regStats(); - this->iew.regStats(); - this->commit.regStats(); -} - - -template <class Impl> -TheISA::MiscReg -AlphaO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscRegNoEffect(misc_reg, tid); -} - -template <class Impl> -TheISA::MiscReg -AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscReg(misc_reg, tid); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, - unsigned tid) -{ - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::setMiscReg(int misc_reg, - const TheISA::MiscReg &val, unsigned tid) -{ - this->regFile.setMiscReg(misc_reg, val, tid); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::squashFromTC(unsigned tid) -{ - this->thread[tid]->inSyscall = true; - this->commit.generateTCEvent(tid); -} - -#if FULL_SYSTEM - -template <class Impl> -void -AlphaO3CPU<Impl>::post_interrupt(int int_num, int index) -{ - BaseCPU::post_interrupt(int_num, index); - - if (this->thread[0]->status() == ThreadContext::Suspended) { - DPRINTF(IPI,"Suspended Processor awoke\n"); - this->threadContexts[0]->activate(); - } -} - -template <class Impl> -Fault -AlphaO3CPU<Impl>::hwrei(unsigned tid) -{ - // Need to clear the lock flag upon returning from an interrupt. - this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); - - this->thread[tid]->kernelStats->hwrei(); - - // FIXME: XXX check for interrupts? XXX - return NoFault; -} - -template <class Impl> -bool -AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) -{ - if (this->thread[tid]->kernelStats) - this->thread[tid]->kernelStats->callpal(palFunc, - this->threadContexts[tid]); - - switch (palFunc) { - case PAL::halt: - halt(); - if (--System::numSystemsRunning == 0) - exitSimLoop("all cpus halted"); - break; - - case PAL::bpt: - case PAL::bugchk: - if (this->system->breakpoint()) - return false; - break; - } - - return true; -} - -template <class Impl> -Fault -AlphaO3CPU<Impl>::getInterrupts() -{ - // Check if there are any outstanding interrupts - return this->interrupts.getInterrupt(this->threadContexts[0]); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::processInterrupts(Fault interrupt) -{ - // Check for interrupts here. For now can copy the code that - // exists within isa_fullsys_traits.hh. Also assume that thread 0 - // is the one that handles the interrupts. - // @todo: Possibly consolidate the interrupt checking code. - // @todo: Allow other threads to handle interrupts. - - assert(interrupt != NoFault); - this->interrupts.updateIntrInfo(this->threadContexts[0]); - - DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->trap(interrupt, 0); -} - -#endif // FULL_SYSTEM - -template <class Impl> -void -AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid) -{ - // Pass the thread's TC into the invoke method. - fault->invoke(this->threadContexts[tid]); -} - -#if !FULL_SYSTEM - -template <class Impl> -void -AlphaO3CPU<Impl>::syscall(int64_t callnum, int tid) -{ - DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); - - DPRINTF(Activity,"Activity: syscall() called.\n"); - - // Temporarily increase this by one to account for the syscall - // instruction. - ++(this->thread[tid]->funcExeInst); - - // Execute the actual syscall. - this->thread[tid]->syscall(callnum); - - // Decrease funcExeInst by one as the normal commit will handle - // incrementing it. - --(this->thread[tid]->funcExeInst); -} - -template <class Impl> -TheISA::IntReg -AlphaO3CPU<Impl>::getSyscallArg(int i, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) -{ - TheISA::setSyscallReturn(return_value, this->tcBase(tid)); -} -#endif diff --git a/src/cpu/o3/alpha/dyn_inst.cc b/src/cpu/o3/alpha/dyn_inst.cc deleted file mode 100644 index 97d2f3d08..000000000 --- a/src/cpu/o3/alpha/dyn_inst.cc +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include "cpu/o3/alpha/dyn_inst_impl.hh" -#include "cpu/o3/alpha/impl.hh" - -// Force instantiation of AlphaDynInst for all the implementations that -// are needed. -template class AlphaDynInst<AlphaSimpleImpl>; diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh deleted file mode 100644 index a6fb7b885..000000000 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_ALPHA_DYN_INST_HH__ -#define __CPU_O3_ALPHA_DYN_INST_HH__ - -#include "arch/isa_traits.hh" -#include "cpu/base_dyn_inst.hh" -#include "cpu/inst_seq.hh" -#include "cpu/o3/alpha/cpu.hh" -#include "cpu/o3/alpha/impl.hh" - -class Packet; - -/** - * Mostly implementation & ISA specific AlphaDynInst. As with most - * other classes in the new CPU model, it is templated on the Impl to - * allow for passing in of all types, such as the CPU type and the ISA - * type. The AlphaDynInst serves as the primary interface to the CPU - * for instructions that are executing. - */ -template <class Impl> -class AlphaDynInst : public BaseDynInst<Impl> -{ - public: - /** Typedef for the CPU. */ - typedef typename Impl::O3CPU O3CPU; - - /** Binary machine instruction type. */ - typedef TheISA::MachInst MachInst; - /** Extended machine instruction type. */ - typedef TheISA::ExtMachInst ExtMachInst; - /** Logical register index type. */ - typedef TheISA::RegIndex RegIndex; - /** Integer register index type. */ - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - /** Misc register index type. */ - typedef TheISA::MiscReg MiscReg; - - enum { - MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs - }; - - public: - /** BaseDynInst constructor given a binary instruction. */ - AlphaDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a binary instruction. */ - AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a static inst pointer. */ - AlphaDynInst(StaticInstPtr &_staticInst); - - /** Executes the instruction.*/ - Fault execute(); - - /** Initiates the access. Only valid for memory operations. */ - Fault initiateAcc(); - - /** Completes the access. Only valid for memory operations. */ - Fault completeAcc(PacketPtr pkt); - - private: - /** Initializes variables. */ - void initVars(); - - public: - /** Reads a miscellaneous register. */ - MiscReg readMiscRegNoEffect(int misc_reg) - { - return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - MiscReg readMiscReg(int misc_reg) - { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegNoEffect(int misc_reg, const MiscReg &val) - { - this->instResult.integer = val; - return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, const MiscReg &val) - { - return this->cpu->setMiscReg(misc_reg, val, - this->threadNumber); - } - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) - { - return this->cpu->readMiscRegNoEffect( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readMiscReg( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) - { - this->instResult.integer = val; - return this->cpu->setMiscRegNoEffect( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscRegOperand(const StaticInst *si, int idx, - const MiscReg &val) - { - return this->cpu->setMiscReg( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - -#if FULL_SYSTEM - /** Calls hardware return from error interrupt. */ - Fault hwrei(); - /** Traps to handle specified fault. */ - void trap(Fault fault); - bool simPalCheck(int palFunc); -#else - /** Calls a syscall. */ - void syscall(int64_t callnum); -#endif - - public: - - // The register accessor methods provide the index of the - // instruction's operand (e.g., 0 or 1), not the architectural - // register index, to simplify the implementation of register - // renaming. We find the architectural register index by indexing - // into the instruction's own operand index table. Note that a - // raw pointer to the StaticInst is provided instead of a - // ref-counted StaticInstPtr to redice overhead. This is fine as - // long as these methods don't copy the pointer into any long-term - // storage (which is pretty hard to imagine they would have reason - // to do). - - uint64_t readIntRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readIntReg(this->_srcRegIdx[idx]); - } - - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - - FloatReg readFloatRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx]); - } - - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); - } - - /** @todo: Make results into arrays so they can handle multiple dest - * registers. - */ - void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) - { - this->cpu->setIntReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntRegOperand(si, idx, val); - } - - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); - } - - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - public: - /** Calculates EA part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault calcEA() - { - return this->staticInst->eaCompInst()->execute(this, this->traceData); - } - - /** Does the memory access part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault memAccess() - { - return this->staticInst->memAccInst()->execute(this, this->traceData); - } -}; - -#endif // __CPU_O3_ALPHA_DYN_INST_HH__ - diff --git a/src/cpu/o3/alpha/impl.hh b/src/cpu/o3/alpha/impl.hh deleted file mode 100644 index b928ae654..000000000 --- a/src/cpu/o3/alpha/impl.hh +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_ALPHA_IMPL_HH__ -#define __CPU_O3_ALPHA_IMPL_HH__ - -#include "arch/alpha/isa_traits.hh" - -#include "cpu/o3/alpha/params.hh" -#include "cpu/o3/cpu_policy.hh" - - -// Forward declarations. -template <class Impl> -class AlphaDynInst; - -template <class Impl> -class AlphaO3CPU; - -/** Implementation specific struct that defines several key types to the - * CPU, the stages within the CPU, the time buffers, and the DynInst. - * The struct defines the ISA, the CPU policy, the specific DynInst, the - * specific O3CPU, and all of the structs from the time buffers to do - * communication. - * This is one of the key things that must be defined for each hardware - * specific CPU implementation. - */ -struct AlphaSimpleImpl -{ - /** The type of MachInst. */ - typedef TheISA::MachInst MachInst; - - /** The CPU policy to be used, which defines all of the CPU stages. */ - typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol; - - /** The DynInst type to be used. */ - typedef AlphaDynInst<AlphaSimpleImpl> DynInst; - - /** The refcounted DynInst pointer to be used. In most cases this is - * what should be used, and not DynInst *. - */ - typedef RefCountingPtr<DynInst> DynInstPtr; - - /** The O3CPU type to be used. */ - typedef AlphaO3CPU<AlphaSimpleImpl> O3CPU; - - /** Same typedef, but for CPUType. BaseDynInst may not always use - * an O3 CPU, so it's clearer to call it CPUType instead in that - * case. - */ - typedef O3CPU CPUType; - - /** The Params to be passed to each stage. */ - typedef AlphaSimpleParams Params; - - enum { - MaxWidth = 8, - MaxThreads = 4 - }; -}; - -/** The O3Impl to be used. */ -typedef AlphaSimpleImpl O3CPUImpl; - -#endif // __CPU_O3_ALPHA_IMPL_HH__ diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh deleted file mode 100644 index 164c25312..000000000 --- a/src/cpu/o3/alpha/params.hh +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_ALPHA_PARAMS_HH__ -#define __CPU_O3_ALPHA_PARAMS_HH__ - -#include "cpu/o3/cpu.hh" -#include "cpu/o3/params.hh" - -//Forward declarations -namespace AlphaISA -{ - class DTB; - class ITB; -} -class MemObject; -class Process; -class System; - -/** - * This file defines the parameters that will be used for the AlphaO3CPU. - * This must be defined externally so that the Impl can have a params class - * defined that it can pass to all of the individual stages. - */ - -class AlphaSimpleParams : public O3Params -{ - public: - - AlphaISA::ITB *itb; - AlphaISA::DTB *dtb; -}; - -#endif // __CPU_O3_ALPHA_PARAMS_HH__ diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc index 0979c5c8f..510109d8a 100644 --- a/src/cpu/o3/base_dyn_inst.cc +++ b/src/cpu/o3/base_dyn_inst.cc @@ -29,11 +29,8 @@ */ #include "cpu/base_dyn_inst_impl.hh" +#include "cpu/o3/cpu.hh" #include "cpu/o3/isa_specific.hh" // Explicit instantiation template class BaseDynInst<O3CPUImpl>; - -template <> -int -BaseDynInst<O3CPUImpl>::instcount = 0; diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh index 3c4c8e478..b32d2bd23 100644 --- a/src/cpu/o3/bpred_unit.hh +++ b/src/cpu/o3/bpred_unit.hh @@ -43,6 +43,8 @@ #include <list> +class DerivO3CPUParams; + /** * Basically a wrapper class to hold both the branch predictor * and the BTB. @@ -51,7 +53,6 @@ template<class Impl> class BPredUnit { private: - typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; enum PredType { @@ -61,12 +62,16 @@ class BPredUnit PredType predictor; + const std::string _name; + public: /** * @param params The params object, that has the size of the BP and BTB. */ - BPredUnit(Params *params); + BPredUnit(DerivO3CPUParams *params); + + const std::string &name() const { return _name; } /** * Registers statistics. @@ -236,21 +241,21 @@ class BPredUnit ReturnAddrStack RAS[Impl::MaxThreads]; /** Stat for number of BP lookups. */ - Stats::Scalar<> lookups; + Stats::Scalar lookups; /** Stat for number of conditional branches predicted. */ - Stats::Scalar<> condPredicted; + Stats::Scalar condPredicted; /** Stat for number of conditional branches predicted incorrectly. */ - Stats::Scalar<> condIncorrect; + Stats::Scalar condIncorrect; /** Stat for number of BTB lookups. */ - Stats::Scalar<> BTBLookups; + Stats::Scalar BTBLookups; /** Stat for number of BTB hits. */ - Stats::Scalar<> BTBHits; + Stats::Scalar BTBHits; /** Stat for number of times the BTB is correct. */ - Stats::Scalar<> BTBCorrect; + Stats::Scalar BTBCorrect; /** Stat for number of times the RAS is used to get a target. */ - Stats::Scalar<> usedRAS; + Stats::Scalar usedRAS; /** Stat for number of times the RAS is incorrect. */ - Stats::Scalar<> RASIncorrect; + Stats::Scalar RASIncorrect; }; #endif // __CPU_O3_BPRED_UNIT_HH__ diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh index 84c50b4da..2fa59280d 100644 --- a/src/cpu/o3/bpred_unit_impl.hh +++ b/src/cpu/o3/bpred_unit_impl.hh @@ -34,11 +34,14 @@ #include "base/traceflags.hh" #include "cpu/o3/bpred_unit.hh" +#include "params/DerivO3CPU.hh" + template<class Impl> -BPredUnit<Impl>::BPredUnit(Params *params) - : BTB(params->BTBEntries, - params->BTBTagSize, - params->instShiftAmt) +BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params) + : _name(params->name + ".BPredUnit"), + BTB(params->BTBEntries, + params->BTBTagSize, + params->instShiftAmt) { // Setup the selected predictor. if (params->predType == "local") { @@ -71,43 +74,43 @@ void BPredUnit<Impl>::regStats() { lookups - .name(name() + ".BPredUnit.lookups") + .name(name() + ".lookups") .desc("Number of BP lookups") ; condPredicted - .name(name() + ".BPredUnit.condPredicted") + .name(name() + ".condPredicted") .desc("Number of conditional branches predicted") ; condIncorrect - .name(name() + ".BPredUnit.condIncorrect") + .name(name() + ".condIncorrect") .desc("Number of conditional branches incorrect") ; BTBLookups - .name(name() + ".BPredUnit.BTBLookups") + .name(name() + ".BTBLookups") .desc("Number of BTB lookups") ; BTBHits - .name(name() + ".BPredUnit.BTBHits") + .name(name() + ".BTBHits") .desc("Number of BTB hits") ; BTBCorrect - .name(name() + ".BPredUnit.BTBCorrect") + .name(name() + ".BTBCorrect") .desc("Number of correct BTB predictions (this stat may not " "work properly.") ; usedRAS - .name(name() + ".BPredUnit.usedRAS") + .name(name() + ".usedRAS") .desc("Number of times the RAS was used to get a target.") ; RASIncorrect - .name(name() + ".BPredUnit.RASInCorrect") + .name(name() + ".RASInCorrect") .desc("Number of incorrect RAS predictions.") ; } diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 80e42fa8b..f21c14569 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -37,6 +37,8 @@ #include "cpu/exetrace.hh" #include "cpu/inst_seq.hh" +class DerivO3CPUParams; + template <class> class O3ThreadState; @@ -69,7 +71,6 @@ class DefaultCommit // Typedefs from the Impl. typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::Params Params; typedef typename Impl::CPUPol CPUPol; typedef typename CPUPol::RenameMap RenameMap; @@ -136,7 +137,7 @@ class DefaultCommit public: /** Construct a DefaultCommit with the given parameters. */ - DefaultCommit(O3CPU *_cpu, Params *params); + DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); /** Returns the name of the DefaultCommit. */ std::string name() const; @@ -451,40 +452,40 @@ class DefaultCommit void updateComInstStats(DynInstPtr &inst); /** Stat for the total number of committed instructions. */ - Stats::Scalar<> commitCommittedInsts; + Stats::Scalar commitCommittedInsts; /** Stat for the total number of squashed instructions discarded by commit. */ - Stats::Scalar<> commitSquashedInsts; + Stats::Scalar commitSquashedInsts; /** Stat for the total number of times commit is told to squash. * @todo: Actually increment this stat. */ - Stats::Scalar<> commitSquashEvents; + Stats::Scalar commitSquashEvents; /** Stat for the total number of times commit has had to stall due to a non- * speculative instruction reaching the head of the ROB. */ - Stats::Scalar<> commitNonSpecStalls; + Stats::Scalar commitNonSpecStalls; /** Stat for the total number of branch mispredicts that caused a squash. */ - Stats::Scalar<> branchMispredicts; + Stats::Scalar branchMispredicts; /** Distribution of the number of committed instructions each cycle. */ - Stats::Distribution<> numCommittedDist; + Stats::Distribution numCommittedDist; /** Total number of instructions committed. */ - Stats::Vector<> statComInst; + Stats::Vector statComInst; /** Total number of software prefetches committed. */ - Stats::Vector<> statComSwp; + Stats::Vector statComSwp; /** Stat for the total number of committed memory references. */ - Stats::Vector<> statComRefs; + Stats::Vector statComRefs; /** Stat for the total number of committed loads. */ - Stats::Vector<> statComLoads; + Stats::Vector statComLoads; /** Total number of committed memory barriers. */ - Stats::Vector<> statComMembars; + Stats::Vector statComMembars; /** Total number of committed branches. */ - Stats::Vector<> statComBranches; + Stats::Vector statComBranches; /** Number of cycles where the commit bandwidth limit is reached. */ - Stats::Scalar<> commitEligibleSamples; + Stats::Scalar commitEligibleSamples; /** Number of instructions not committed due to bandwidth limits. */ - Stats::Vector<> commitEligible; + Stats::Vector commitEligible; }; #endif // __CPU_O3_COMMIT_HH__ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index ee0f2bb59..7cd88b49b 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -36,6 +36,7 @@ #include <string> #include "arch/utility.hh" +#include "base/cp_annotate.hh" #include "base/loader/symtab.hh" #include "base/timebuf.hh" #include "cpu/exetrace.hh" @@ -46,12 +47,14 @@ #include "cpu/checker/cpu.hh" #endif +#include "params/DerivO3CPU.hh" + template <class Impl> DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid) - : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) + : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) { - this->setFlags(Event::AutoDelete); + this->setFlags(AutoDelete); } template <class Impl> @@ -71,7 +74,7 @@ DefaultCommit<Impl>::TrapEvent::description() const } template <class Impl> -DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params) +DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) : cpu(_cpu), squashCounter(0), iewToCommitDelay(params->iewToCommitDelay), @@ -80,7 +83,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params) fetchToCommitDelay(params->commitToFetchDelay), renameWidth(params->renameWidth), commitWidth(params->commitWidth), - numThreads(params->numberOfThreads), + numThreads(params->numThreads), drainPending(false), switchedOut(false), trapLatency(params->trapLatency) @@ -460,7 +463,7 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid) TrapEvent *trap = new TrapEvent(this, tid); - trap->schedule(curTick + trapLatency); + cpu->schedule(trap, curTick + trapLatency); trapInFlight[tid] = true; } @@ -663,7 +666,7 @@ DefaultCommit<Impl>::handleInterrupt() DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } } else if (commitStatus[0] != TrapPending && - cpu->check_interrupts(cpu->tcBase(0)) && + cpu->checkInterrupts(cpu->tcBase(0)) && !trapSquash[0] && !tcSquash[0]) { // Process interrupts if interrupts are enabled, not in PAL @@ -693,7 +696,7 @@ DefaultCommit<Impl>::commit() // Check for any interrupt, and start processing it. Or if we // have an outstanding interrupt and are at a point when it is // valid to take an interrupt, process it. - if (cpu->check_interrupts(cpu->tcBase(0))) { + if (cpu->checkInterrupts(cpu->tcBase(0))) { handleInterrupt(); } #endif // FULL_SYSTEM @@ -812,7 +815,7 @@ DefaultCommit<Impl>::commit() // @todo: Make this handle multi-cycle communication between // commit and IEW. if (checkEmptyROB[tid] && rob->isEmpty(tid) && - !iewStage->hasStoresToWB() && !committedStores[tid]) { + !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { checkEmptyROB[tid] = false; toIEW->commitInfo[tid].usedROB = true; toIEW->commitInfo[tid].emptyROB = true; @@ -966,7 +969,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", head_inst->seqNum, head_inst->readPC()); - if (inst_num > 0 || iewStage->hasStoresToWB()) { + if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { DPRINTF(Commit, "Waiting for all stores to writeback.\n"); return false; } @@ -981,7 +984,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) return false; } else if (head_inst->isLoad()) { - if (inst_num > 0 || iewStage->hasStoresToWB()) { + if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { DPRINTF(Commit, "Waiting for all stores to writeback.\n"); return false; } @@ -1036,7 +1039,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", head_inst->seqNum, head_inst->readPC()); - if (iewStage->hasStoresToWB() || inst_num > 0) { + if (iewStage->hasStoresToWB(tid) || inst_num > 0) { DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); return false; } @@ -1095,6 +1098,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) if (node) thread[tid]->profileNode = node; } + if (CPA::available()) { + if (head_inst->isControl()) { + ThreadContext *tc = thread[tid]->getTC(); + CPA::cpa()->swAutoBegin(tc, head_inst->readNextPC()); + } + } #endif if (head_inst->traceData) { diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c75a08213..1d7fb97c0 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -37,6 +37,7 @@ #include "cpu/thread_context.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/o3/cpu.hh" +#include "cpu/o3/thread_context.hh" #include "enums/MemoryMode.hh" #include "sim/core.hh" #include "sim/stat_control.hh" @@ -52,10 +53,16 @@ #include "cpu/checker/cpu.hh" #endif +#if THE_ISA == ALPHA_ISA +#include "arch/alpha/osfpal.hh" +#endif + +class BaseCPUParams; + using namespace TheISA; -BaseO3CPU::BaseO3CPU(Params *params) - : BaseCPU(params), cpu_id(0) +BaseO3CPU::BaseO3CPU(BaseCPUParams *params) + : BaseCPU(params) { } @@ -67,7 +74,7 @@ BaseO3CPU::regStats() template <class Impl> FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) - : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) + : Event(CPU_Tick_Pri), cpu(c) { } @@ -87,7 +94,7 @@ FullO3CPU<Impl>::TickEvent::description() const template <class Impl> FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() - : Event(&mainEventQueue, CPU_Switch_Pri) + : Event(CPU_Switch_Pri) { } @@ -116,7 +123,7 @@ FullO3CPU<Impl>::ActivateThreadEvent::description() const template <class Impl> FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() - : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) + : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) { } @@ -147,31 +154,34 @@ FullO3CPU<Impl>::DeallocateContextEvent::description() const } template <class Impl> -FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) +FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) : BaseO3CPU(params), itb(params->itb), dtb(params->dtb), tickEvent(this), +#ifndef NDEBUG + instcount(0), +#endif removeInstsThisCycle(false), - fetch(o3_cpu, params), - decode(o3_cpu, params), - rename(o3_cpu, params), - iew(o3_cpu, params), - commit(o3_cpu, params), + fetch(this, params), + decode(this, params), + rename(this, params), + iew(this, params), + commit(this, params), - regFile(o3_cpu, params->numPhysIntRegs, + regFile(this, params->numPhysIntRegs, params->numPhysFloatRegs), - freeList(params->numberOfThreads, + freeList(params->numThreads, TheISA::NumIntRegs, params->numPhysIntRegs, TheISA::NumFloatRegs, params->numPhysFloatRegs), - rob(o3_cpu, + rob(this, params->numROBEntries, params->squashWidth, params->smtROBPolicy, params->smtROBThreshold, - params->numberOfThreads), + params->numThreads), - scoreboard(params->numberOfThreads, + scoreboard(params->numThreads, TheISA::NumIntRegs, params->numPhysIntRegs, TheISA::NumFloatRegs, params->numPhysFloatRegs, TheISA::NumMiscRegs * number_of_threads, @@ -182,7 +192,7 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) decodeQueue(params->backComSize, params->forwardComSize), renameQueue(params->backComSize, params->forwardComSize), iewQueue(params->backComSize, params->forwardComSize), - activityRec(NumStages, + activityRec(name(), NumStages, params->backComSize + params->forwardComSize, params->activity), @@ -192,7 +202,7 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) physmem(system->physmem), #endif // FULL_SYSTEM drainCount(0), - deferRegistration(params->deferRegistration), + deferRegistration(params->defer_registration), numThreads(number_of_threads) { if (!deferRegistration) { @@ -336,6 +346,78 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) //} contextSwitch = false; + DPRINTF(O3CPU, "Creating O3CPU object.\n"); + + // Setup any thread state. + this->thread.resize(this->numThreads); + + for (int i = 0; i < this->numThreads; ++i) { +#if FULL_SYSTEM + // SMT is not supported in FS mode yet. + assert(this->numThreads == 1); + this->thread[i] = new Thread(this, 0); + this->thread[i]->setStatus(ThreadContext::Suspended); +#else + if (i < params->workload.size()) { + DPRINTF(O3CPU, "Workload[%i] process is %#x", + i, this->thread[i]); + this->thread[i] = new typename FullO3CPU<Impl>::Thread( + (typename Impl::O3CPU *)(this), + i, params->workload[i], i); + + this->thread[i]->setStatus(ThreadContext::Suspended); + + //usedTids[i] = true; + //threadMap[i] = i; + } else { + //Allocate Empty thread so M5 can use later + //when scheduling threads to CPU + Process* dummy_proc = NULL; + + this->thread[i] = new typename FullO3CPU<Impl>::Thread( + (typename Impl::O3CPU *)(this), + i, dummy_proc, i); + //usedTids[i] = false; + } +#endif // !FULL_SYSTEM + + ThreadContext *tc; + + // Setup the TC that will serve as the interface to the threads/CPU. + O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; + + tc = o3_tc; + + // If we're using a checker, then the TC should be the + // CheckerThreadContext. +#if USE_CHECKER + if (params->checker) { + tc = new CheckerThreadContext<O3ThreadContext<Impl> >( + o3_tc, this->checker); + } +#endif + + o3_tc->cpu = (typename Impl::O3CPU *)(this); + assert(o3_tc->cpu); + o3_tc->thread = this->thread[i]; + +#if FULL_SYSTEM + // Setup quiesce event. + this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); +#endif + // Give the thread the TC. + this->thread[i]->tc = tc; + + // Add the TC to the CPU's list of TC's. + this->threadContexts.push_back(tc); + } + + for (int i=0; i < this->numThreads; i++) { + this->thread[i]->setFuncExeInst(0); + } + + lockAddr = 0; + lockFlag = false; } template <class Impl> @@ -345,7 +427,7 @@ FullO3CPU<Impl>::~FullO3CPU() template <class Impl> void -FullO3CPU<Impl>::fullCPURegStats() +FullO3CPU<Impl>::regStats() { BaseO3CPU::regStats(); @@ -399,6 +481,11 @@ FullO3CPU<Impl>::fullCPURegStats() .precision(6); totalIpc = totalCommittedInsts / numCycles; + this->fetch.regStats(); + this->decode.regStats(); + this->rename.regStats(); + this->iew.regStats(); + this->commit.regStats(); } template <class Impl> @@ -463,7 +550,7 @@ FullO3CPU<Impl>::tick() lastRunningCycle = curTick; timesIdled++; } else { - tickEvent.schedule(nextCycle(curTick + ticks(1))); + schedule(tickEvent, nextCycle(curTick + ticks(1))); DPRINTF(O3CPU, "Scheduling next tick!\n"); } } @@ -471,16 +558,13 @@ FullO3CPU<Impl>::tick() #if !FULL_SYSTEM updateThreadPriority(); #endif - } template <class Impl> void FullO3CPU<Impl>::init() { - if (!deferRegistration) { - registerThreadContexts(); - } + BaseCPU::init(); // Set inSyscall so that the CPU doesn't squash when initially // setting up registers. @@ -499,7 +583,7 @@ FullO3CPU<Impl>::init() } #if FULL_SYSTEM - TheISA::initCPU(src_tc, src_tc->readCpuId()); + TheISA::initCPU(src_tc, src_tc->contextId()); #endif } @@ -602,7 +686,7 @@ FullO3CPU<Impl>::suspendContext(int tid) DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); bool deallocated = deallocateContext(tid, false, 1); // If this was the last thread then unschedule the tick event. - if (activeThreads.size() == 1 && !deallocated || + if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0) unscheduleTickEvent(); _status = Idle; @@ -782,18 +866,116 @@ FullO3CPU<Impl>::activateWhenReady(int tid) #if FULL_SYSTEM template <class Impl> +Fault +FullO3CPU<Impl>::hwrei(unsigned tid) +{ +#if THE_ISA == ALPHA_ISA + // Need to clear the lock flag upon returning from an interrupt. + this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); + + this->thread[tid]->kernelStats->hwrei(); + + // FIXME: XXX check for interrupts? XXX +#endif + return NoFault; +} + +template <class Impl> +bool +FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) +{ +#if THE_ISA == ALPHA_ISA + if (this->thread[tid]->kernelStats) + this->thread[tid]->kernelStats->callpal(palFunc, + this->threadContexts[tid]); + + switch (palFunc) { + case PAL::halt: + halt(); + if (--System::numSystemsRunning == 0) + exitSimLoop("all cpus halted"); + break; + + case PAL::bpt: + case PAL::bugchk: + if (this->system->breakpoint()) + return false; + break; + } +#endif + return true; +} + +template <class Impl> +Fault +FullO3CPU<Impl>::getInterrupts() +{ + // Check if there are any outstanding interrupts + return this->interrupts->getInterrupt(this->threadContexts[0]); +} + +template <class Impl> +void +FullO3CPU<Impl>::processInterrupts(Fault interrupt) +{ + // Check for interrupts here. For now can copy the code that + // exists within isa_fullsys_traits.hh. Also assume that thread 0 + // is the one that handles the interrupts. + // @todo: Possibly consolidate the interrupt checking code. + // @todo: Allow other threads to handle interrupts. + + assert(interrupt != NoFault); + this->interrupts->updateIntrInfo(this->threadContexts[0]); + + DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); + this->trap(interrupt, 0); +} + +template <class Impl> void FullO3CPU<Impl>::updateMemPorts() { // Update all ThreadContext's memory ports (Functional/Virtual // Ports) for (int i = 0; i < thread.size(); ++i) - thread[i]->connectMemPorts(); + thread[i]->connectMemPorts(thread[i]->getTC()); } #endif template <class Impl> void +FullO3CPU<Impl>::trap(Fault fault, unsigned tid) +{ + // Pass the thread's TC into the invoke method. + fault->invoke(this->threadContexts[tid]); +} + +#if !FULL_SYSTEM + +template <class Impl> +void +FullO3CPU<Impl>::syscall(int64_t callnum, int tid) +{ + DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); + + DPRINTF(Activity,"Activity: syscall() called.\n"); + + // Temporarily increase this by one to account for the syscall + // instruction. + ++(this->thread[tid]->funcExeInst); + + // Execute the actual syscall. + this->thread[tid]->syscall(callnum); + + // Decrease funcExeInst by one as the normal commit will handle + // incrementing it. + --(this->thread[tid]->funcExeInst); +} + +#endif + +template <class Impl> +void FullO3CPU<Impl>::serialize(std::ostream &os) { SimObject::State so_state = SimObject::getState(); @@ -891,7 +1073,7 @@ FullO3CPU<Impl>::resume() #endif if (!tickEvent.scheduled()) - tickEvent.schedule(nextCycle()); + schedule(tickEvent, nextCycle()); _status = Running; } @@ -984,11 +1166,41 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) ThreadContext *tc = threadContexts[i]; if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; - tickEvent.schedule(nextCycle()); + schedule(tickEvent, nextCycle()); } } if (!tickEvent.scheduled()) - tickEvent.schedule(nextCycle()); + schedule(tickEvent, nextCycle()); +} + +template <class Impl> +TheISA::MiscReg +FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) +{ + return this->regFile.readMiscRegNoEffect(misc_reg, tid); +} + +template <class Impl> +TheISA::MiscReg +FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) +{ + return this->regFile.readMiscReg(misc_reg, tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, + const TheISA::MiscReg &val, unsigned tid) +{ + this->regFile.setMiscRegNoEffect(misc_reg, val, tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setMiscReg(int misc_reg, + const TheISA::MiscReg &val, unsigned tid) +{ + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> @@ -1210,6 +1422,14 @@ FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) } template <class Impl> +void +FullO3CPU<Impl>::squashFromTC(unsigned tid) +{ + this->thread[tid]->inSyscall = true; + this->commit.generateTCEvent(tid); +} + +template <class Impl> typename FullO3CPU<Impl>::ListIt FullO3CPU<Impl>::addInst(DynInstPtr &inst) { @@ -1419,9 +1639,24 @@ FullO3CPU<Impl>::wakeCPU() idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); numCycles += tickToCycles((curTick - 1) - lastRunningCycle); - tickEvent.schedule(nextCycle()); + schedule(tickEvent, nextCycle()); } +#if FULL_SYSTEM +template <class Impl> +void +FullO3CPU<Impl>::wakeup() +{ + if (this->thread[0]->status() != ThreadContext::Suspended) + return; + + this->wakeCPU(); + + DPRINTF(Quiesce, "Suspended Processor woken\n"); + this->threadContexts[0]->activate(); +} +#endif + template <class Impl> int FullO3CPU<Impl>::getFreeTid() diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 61d7dcf22..942970f5f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -53,6 +53,8 @@ //#include "cpu/o3/thread_context.hh" #include "sim/process.hh" +#include "params/DerivO3CPU.hh" + template <class> class Checker; class ThreadContext; @@ -63,24 +65,15 @@ class Checkpoint; class MemObject; class Process; +class BaseCPUParams; + class BaseO3CPU : public BaseCPU { //Stuff that's pretty ISA independent will go here. public: - typedef BaseCPU::Params Params; - - BaseO3CPU(Params *params); + BaseO3CPU(BaseCPUParams *params); void regStats(); - - /** Sets this CPU's ID. */ - void setCpuId(int id) { cpu_id = id; } - - /** Reads this CPU's ID. */ - int readCpuId() { return cpu_id; } - - protected: - int cpu_id; }; /** @@ -96,8 +89,8 @@ class FullO3CPU : public BaseO3CPU typedef typename Impl::CPUPol CPUPolicy; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; - typedef typename Impl::Params Params; + typedef O3ThreadState<Impl> ImplState; typedef O3ThreadState<Impl> Thread; typedef typename std::list<DynInstPtr>::iterator ListIt; @@ -146,9 +139,9 @@ class FullO3CPU : public BaseO3CPU void scheduleTickEvent(int delay) { if (tickEvent.squashed()) - tickEvent.reschedule(nextCycle(curTick + ticks(delay))); + reschedule(tickEvent, nextCycle(curTick + ticks(delay))); else if (!tickEvent.scheduled()) - tickEvent.schedule(nextCycle(curTick + ticks(delay))); + schedule(tickEvent, nextCycle(curTick + ticks(delay))); } /** Unschedule tick event, regardless of its current state. */ @@ -186,11 +179,11 @@ class FullO3CPU : public BaseO3CPU { // Schedule thread to activate, regardless of its current state. if (activateThreadEvent[tid].squashed()) - activateThreadEvent[tid]. - reschedule(nextCycle(curTick + ticks(delay))); + reschedule(activateThreadEvent[tid], + nextCycle(curTick + ticks(delay))); else if (!activateThreadEvent[tid].scheduled()) - activateThreadEvent[tid]. - schedule(nextCycle(curTick + ticks(delay))); + schedule(activateThreadEvent[tid], + nextCycle(curTick + ticks(delay))); } /** Unschedule actiavte thread event, regardless of its current state. */ @@ -237,11 +230,11 @@ class FullO3CPU : public BaseO3CPU { // Schedule thread to activate, regardless of its current state. if (deallocateContextEvent[tid].squashed()) - deallocateContextEvent[tid]. - reschedule(nextCycle(curTick + ticks(delay))); + reschedule(deallocateContextEvent[tid], + nextCycle(curTick + ticks(delay))); else if (!deallocateContextEvent[tid].scheduled()) - deallocateContextEvent[tid]. - schedule(nextCycle(curTick + ticks(delay))); + schedule(deallocateContextEvent[tid], + nextCycle(curTick + ticks(delay))); } /** Unschedule thread deallocation in CPU */ @@ -256,12 +249,12 @@ class FullO3CPU : public BaseO3CPU public: /** Constructs a CPU with the given parameters. */ - FullO3CPU(O3CPU *o3_cpu, Params *params); + FullO3CPU(DerivO3CPUParams *params); /** Destructor. */ ~FullO3CPU(); /** Registers statistics. */ - void fullCPURegStats(); + void regStats(); void demapPage(Addr vaddr, uint64_t asn) { @@ -279,24 +272,6 @@ class FullO3CPU : public BaseO3CPU this->dtb->demapPage(vaddr, asn); } - /** Translates instruction requestion. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return this->itb->translate(req, thread->getTC()); - } - - /** Translates data read request. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), false); - } - - /** Translates data write request. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), true); - } - /** Returns a specific port. */ Port *getPort(const std::string &if_name, int idx); @@ -367,12 +342,12 @@ class FullO3CPU : public BaseO3CPU virtual void unserialize(Checkpoint *cp, const std::string §ion); public: - /** Executes a syscall on this cycle. - * --------------------------------------- - * Note: this is a virtual function. CPU-Specific - * functionality defined in derived classes +#if !FULL_SYSTEM + /** Executes a syscall. + * @todo: Determine if this needs to be virtual. */ - virtual void syscall(int tid) { panic("Unimplemented!"); } + void syscall(int64_t callnum, int tid); +#endif /** Starts draining the CPU's pipeline of all instructions in * order to stop all memory accesses. */ @@ -394,7 +369,24 @@ class FullO3CPU : public BaseO3CPU InstSeqNum getAndIncrementInstSeq() { return globalSeqNum++; } + /** Traps to handle given fault. */ + void trap(Fault fault, unsigned tid); + #if FULL_SYSTEM + /** HW return from error interrupt. */ + Fault hwrei(unsigned tid); + + bool simPalCheck(int palFunc, unsigned tid); + + /** Returns the Fault for any valid interrupt. */ + Fault getInterrupts(); + + /** Processes any an interrupt fault. */ + void processInterrupts(Fault interrupt); + + /** Halts the CPU. */ + void halt() { panic("Halt not implemented!\n"); } + /** Update the Virt and Phys ports of all ThreadContexts to * reflect change in memory connections. */ void updateMemPorts(); @@ -424,6 +416,24 @@ class FullO3CPU : public BaseO3CPU #endif /** Register accessors. Index refers to the physical register index. */ + + /** Reads a miscellaneous register. */ + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); + + /** Reads a misc. register, including any side effects the read + * might have as defined by the architecture. + */ + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + + /** Sets a miscellaneous register. */ + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + + /** Sets a misc. register, including any side effects the write + * might have as defined by the architecture. + */ + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, + unsigned tid); + uint64_t readIntReg(int reg_idx); TheISA::FloatReg readFloatReg(int reg_idx); @@ -495,6 +505,12 @@ class FullO3CPU : public BaseO3CPU /** Sets the commit next micro PC of a specific thread. */ void setNextMicroPC(Addr val, unsigned tid); + /** Initiates a squash of all in-flight instructions for a given + * thread. The source of the squash is an external update of + * state through the TC. + */ + void squashFromTC(unsigned tid); + /** Function to add instruction onto the head of the list of the * instructions. Used when new instructions are fetched. */ @@ -528,6 +544,11 @@ class FullO3CPU : public BaseO3CPU void dumpInsts(); public: +#ifndef NDEBUG + /** Count of total number of dynamic instructions in flight. */ + int instcount; +#endif + /** List of all the instructions in flight. */ std::list<DynInstPtr> instList; @@ -648,6 +669,10 @@ class FullO3CPU : public BaseO3CPU /** Wakes the CPU, rescheduling the CPU if it's not already active. */ void wakeCPU(); +#if FULL_SYSTEM + virtual void wakeup(); +#endif + /** Gets a free thread id. Use if thread ids change across system. */ int getFreeTid(); @@ -710,14 +735,33 @@ class FullO3CPU : public BaseO3CPU /** Available thread ids in the cpu*/ std::vector<unsigned> tids; + /** CPU read function, forwards read to LSQ. */ + template <class T> + Fault read(RequestPtr &req, T &data, int load_idx) + { + return this->iew.ldstQueue.read(req, data, load_idx); + } + + /** CPU write function, forwards write to LSQ. */ + template <class T> + Fault write(RequestPtr &req, T &data, int store_idx) + { + return this->iew.ldstQueue.write(req, data, store_idx); + } + + Addr lockAddr; + + /** Temporary fix for the lock flag, works in the UP case. */ + bool lockFlag; + /** Stat for total number of times the CPU is descheduled. */ - Stats::Scalar<> timesIdled; + Stats::Scalar timesIdled; /** Stat for total number of cycles the CPU spends descheduled. */ - Stats::Scalar<> idleCycles; + Stats::Scalar idleCycles; /** Stat for the number of committed instructions per thread. */ - Stats::Vector<> committedInsts; + Stats::Vector committedInsts; /** Stat for the total number of committed instructions. */ - Stats::Scalar<> totalCommittedInsts; + Stats::Scalar totalCommittedInsts; /** Stat for the CPI per thread. */ Stats::Formula cpi; /** Stat for the total CPI. */ diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/cpu_builder.cc index 6d61501ac..77d7091ad 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/cpu_builder.cc @@ -28,49 +28,51 @@ * Authors: Kevin Lim */ -#include "arch/alpha/types.hh" -#include "cpu/o3/thread_context.hh" +#include <string> -template <class Impl> -class AlphaTC : public O3ThreadContext<Impl> +#include "config/full_system.hh" +#include "config/use_checker.hh" +#include "cpu/o3/cpu.hh" +#include "cpu/o3/impl.hh" +#include "params/DerivO3CPU.hh" + +class DerivO3CPU : public FullO3CPU<O3CPUImpl> { public: + DerivO3CPU(DerivO3CPUParams *p) + : FullO3CPU<O3CPUImpl>(p) + { } +}; + +DerivO3CPU * +DerivO3CPUParams::create() +{ #if FULL_SYSTEM - /** Returns pointer to the quiesce event. */ - virtual EndQuiesceEvent *getQuiesceEvent() - { - return this->thread->quiesceEvent; - } -#endif + // Full-system only supports a single thread for the moment. + int actual_num_threads = 1; +#else + // In non-full-system mode, we infer the number of threads from + // the workload if it's not explicitly specified. + int actual_num_threads = + (numThreads >= workload.size()) ? numThreads : workload.size(); - virtual uint64_t readNextNPC() - { - return this->readNextPC() + sizeof(TheISA::MachInst); + if (workload.size() == 0) { + fatal("Must specify at least one workload!"); } +#endif - virtual void setNextNPC(uint64_t val) - { - panic("Alpha has no NextNPC!"); - } + numThreads = actual_num_threads; - virtual void changeRegFileContext(TheISA::RegContextParam param, - TheISA::RegContextVal val) - { panic("Not supported on Alpha!"); } + // Default smtFetchPolicy to "RoundRobin", if necessary. + std::string round_robin_policy = "RoundRobin"; + std::string single_thread = "SingleThread"; + if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0) + smtFetchPolicy = round_robin_policy; + else + smtFetchPolicy = smtFetchPolicy; - /** This function exits the thread context in the CPU and returns - * 1 if the CPU has no more active threads (meaning it's OK to exit); - * Used in syscall-emulation mode when a thread executes the 'exit' - * syscall. - */ - virtual int exit() - { - this->deallocate(); + instShiftAmt = 2; - // If there are still threads executing in the system - if (this->cpu->numActiveThreads()) - return 0; // don't exit simulation - else - return 1; // exit simulation - } -}; + return new DerivO3CPU(this); +} diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh index 32a0adcf1..c06c9a201 100644 --- a/src/cpu/o3/cpu_policy.hh +++ b/src/cpu/o3/cpu_policy.hh @@ -65,7 +65,7 @@ struct SimpleCPUPolicy /** Typedef for the branch prediction unit (which includes the BP, * RAS, and BTB). */ - typedef BPredUnit<Impl> BPredUnit; + typedef ::BPredUnit<Impl> BPredUnit; /** Typedef for the register file. Most classes assume a unified * physical register file. */ @@ -75,15 +75,15 @@ struct SimpleCPUPolicy /** Typedef for the rename map. */ typedef SimpleRenameMap RenameMap; /** Typedef for the ROB. */ - typedef ROB<Impl> ROB; + typedef ::ROB<Impl> ROB; /** Typedef for the instruction queue/scheduler. */ typedef InstructionQueue<Impl> IQ; /** Typedef for the memory dependence unit. */ - typedef MemDepUnit<StoreSet, Impl> MemDepUnit; + typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit; /** Typedef for the LSQ. */ - typedef LSQ<Impl> LSQ; + typedef ::LSQ<Impl> LSQ; /** Typedef for the thread-specific LSQ units. */ - typedef LSQUnit<Impl> LSQUnit; + typedef ::LSQUnit<Impl> LSQUnit; /** Typedef for fetch. */ typedef DefaultFetch<Impl> Fetch; @@ -109,7 +109,7 @@ struct SimpleCPUPolicy typedef DefaultIEWDefaultCommit<Impl> IEWStruct; /** The struct for communication within the IEW stage. */ - typedef IssueStruct<Impl> IssueStruct; + typedef ::IssueStruct<Impl> IssueStruct; /** The struct for all backwards communication. */ typedef TimeBufStruct<Impl> TimeStruct; diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh index 3e82033ca..294b5b623 100644 --- a/src/cpu/o3/decode.hh +++ b/src/cpu/o3/decode.hh @@ -36,6 +36,8 @@ #include "base/statistics.hh" #include "base/timebuf.hh" +class DerivO3CPUParams; + /** * DefaultDecode class handles both single threaded and SMT * decode. Its width is specified by the parameters; each cycles it @@ -50,7 +52,6 @@ class DefaultDecode // Typedefs from the Impl. typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::Params Params; typedef typename Impl::CPUPol CPUPol; // Typedefs from the CPU policy. @@ -86,7 +87,7 @@ class DefaultDecode public: /** DefaultDecode constructor. */ - DefaultDecode(O3CPU *_cpu, Params *params); + DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params); /** Returns the name of decode. */ std::string name() const; @@ -287,27 +288,27 @@ class DefaultDecode /** Stat for total number of idle cycles. */ - Stats::Scalar<> decodeIdleCycles; + Stats::Scalar decodeIdleCycles; /** Stat for total number of blocked cycles. */ - Stats::Scalar<> decodeBlockedCycles; + Stats::Scalar decodeBlockedCycles; /** Stat for total number of normal running cycles. */ - Stats::Scalar<> decodeRunCycles; + Stats::Scalar decodeRunCycles; /** Stat for total number of unblocking cycles. */ - Stats::Scalar<> decodeUnblockCycles; + Stats::Scalar decodeUnblockCycles; /** Stat for total number of squashing cycles. */ - Stats::Scalar<> decodeSquashCycles; + Stats::Scalar decodeSquashCycles; /** Stat for number of times a branch is resolved at decode. */ - Stats::Scalar<> decodeBranchResolved; + Stats::Scalar decodeBranchResolved; /** Stat for number of times a branch mispredict is detected. */ - Stats::Scalar<> decodeBranchMispred; + Stats::Scalar decodeBranchMispred; /** Stat for number of times decode detected a non-control instruction * incorrectly predicted as a branch. */ - Stats::Scalar<> decodeControlMispred; + Stats::Scalar decodeControlMispred; /** Stat for total number of decoded instructions. */ - Stats::Scalar<> decodeDecodedInsts; + Stats::Scalar decodeDecodedInsts; /** Stat for total number of squashed instructions. */ - Stats::Scalar<> decodeSquashedInsts; + Stats::Scalar decodeSquashedInsts; }; #endif // __CPU_O3_DECODE_HH__ diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index ce6738456..015bc8d7f 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -30,15 +30,17 @@ #include "cpu/o3/decode.hh" +#include "params/DerivO3CPU.hh" + template<class Impl> -DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params) +DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) : cpu(_cpu), renameToDecodeDelay(params->renameToDecodeDelay), iewToDecodeDelay(params->iewToDecodeDelay), commitToDecodeDelay(params->commitToDecodeDelay), fetchToDecodeDelay(params->fetchToDecodeDelay), decodeWidth(params->decodeWidth), - numThreads(params->numberOfThreads) + numThreads(params->numThreads) { _status = Inactive; diff --git a/src/cpu/o3/sparc/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc index 984b58f4b..d828ef1b0 100644 --- a/src/cpu/o3/sparc/dyn_inst.cc +++ b/src/cpu/o3/dyn_inst.cc @@ -28,9 +28,9 @@ * Authors: Gabe Black */ -#include "cpu/o3/sparc/dyn_inst_impl.hh" -#include "cpu/o3/sparc/impl.hh" +#include "cpu/o3/dyn_inst_impl.hh" +#include "cpu/o3/impl.hh" -// Force instantiation of SparcDynInst for all the implementations that +// Force instantiation of BaseO3DynInst for all the implementations that // are needed. -template class SparcDynInst<SparcSimpleImpl>; +template class BaseO3DynInst<O3CPUImpl>; diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index a1f9e0591..292547b6b 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,36 +25,266 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Korey Sewell + * Authors: Kevin Lim */ #ifndef __CPU_O3_DYN_INST_HH__ #define __CPU_O3_DYN_INST_HH__ -#include "arch/isa_specific.hh" - -#if THE_ISA == ALPHA_ISA - template <class Impl> class AlphaDynInst; - struct AlphaSimpleImpl; - typedef AlphaDynInst<AlphaSimpleImpl> O3DynInst; -#elif THE_ISA == MIPS_ISA - template <class Impl> class MipsDynInst; - struct MipsSimpleImpl; - typedef MipsDynInst<MipsSimpleImpl> O3DynInst; -#elif THE_ISA == SPARC_ISA - template <class Impl> class SparcDynInst; - struct SparcSimpleImpl; - typedef SparcDynInst<SparcSimpleImpl> O3DynInst; -#elif THE_ISA == X86_ISA - template <class Impl> class X86DynInst; - struct X86SimpleImpl; - typedef X86DynInst<X86SimpleImpl> O3DynInst; -#elif THE_ISA == ARM_ISA - template <class Impl> class ArmDynInst; - struct ArmSimpleImpl; - typedef ArmDynInst<ArmSimpleImpl> O3DynInst; +#include "arch/isa_traits.hh" +#include "cpu/base_dyn_inst.hh" +#include "cpu/inst_seq.hh" +#include "cpu/o3/cpu.hh" +#include "cpu/o3/isa_specific.hh" + +class Packet; + +/** + * Mostly implementation & ISA specific AlphaDynInst. As with most + * other classes in the new CPU model, it is templated on the Impl to + * allow for passing in of all types, such as the CPU type and the ISA + * type. The AlphaDynInst serves as the primary interface to the CPU + * for instructions that are executing. + */ +template <class Impl> +class BaseO3DynInst : public BaseDynInst<Impl> +{ + public: + /** Typedef for the CPU. */ + typedef typename Impl::O3CPU O3CPU; + + /** Binary machine instruction type. */ + typedef TheISA::MachInst MachInst; + /** Extended machine instruction type. */ + typedef TheISA::ExtMachInst ExtMachInst; + /** Logical register index type. */ + typedef TheISA::RegIndex RegIndex; + /** Integer register index type. */ + typedef TheISA::IntReg IntReg; + typedef TheISA::FloatReg FloatReg; + typedef TheISA::FloatRegBits FloatRegBits; + /** Misc register index type. */ + typedef TheISA::MiscReg MiscReg; + + enum { + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs + }; + + public: + /** BaseDynInst constructor given a binary instruction. */ + BaseO3DynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu); + + /** BaseDynInst constructor given a binary instruction. */ + BaseO3DynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu); + + /** BaseDynInst constructor given a static inst pointer. */ + BaseO3DynInst(StaticInstPtr &_staticInst); + + /** Executes the instruction.*/ + Fault execute(); + + /** Initiates the access. Only valid for memory operations. */ + Fault initiateAcc(); + + /** Completes the access. Only valid for memory operations. */ + Fault completeAcc(PacketPtr pkt); + + private: + /** Initializes variables. */ + void initVars(); + + public: + /** Reads a miscellaneous register. */ + MiscReg readMiscRegNoEffect(int misc_reg) + { + return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); + } + + /** Reads a misc. register, including any side-effects the read + * might have as defined by the architecture. + */ + MiscReg readMiscReg(int misc_reg) + { + return this->cpu->readMiscReg(misc_reg, this->threadNumber); + } + + /** Sets a misc. register. */ + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + { + this->instResult.integer = val; + return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); + } + + /** Sets a misc. register, including any side-effects the write + * might have as defined by the architecture. + */ + void setMiscReg(int misc_reg, const MiscReg &val) + { + return this->cpu->setMiscReg(misc_reg, val, + this->threadNumber); + } + + /** Reads a miscellaneous register. */ + TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) + { + return this->cpu->readMiscRegNoEffect( + si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + this->threadNumber); + } + + /** Reads a misc. register, including any side-effects the read + * might have as defined by the architecture. + */ + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + { + return this->cpu->readMiscReg( + si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + this->threadNumber); + } + + /** Sets a misc. register. */ + void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) + { + this->instResult.integer = val; + return this->cpu->setMiscRegNoEffect( + si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + val, this->threadNumber); + } + + /** Sets a misc. register, including any side-effects the write + * might have as defined by the architecture. + */ + void setMiscRegOperand(const StaticInst *si, int idx, + const MiscReg &val) + { + return this->cpu->setMiscReg( + si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + val, this->threadNumber); + } + +#if FULL_SYSTEM + /** Calls hardware return from error interrupt. */ + Fault hwrei(); + /** Traps to handle specified fault. */ + void trap(Fault fault); + bool simPalCheck(int palFunc); #else - #error "O3DynInst not defined for this ISA" + /** Calls a syscall. */ + void syscall(int64_t callnum); #endif -#endif // __CPU_O3_DYN_INST_HH__ + public: + + // The register accessor methods provide the index of the + // instruction's operand (e.g., 0 or 1), not the architectural + // register index, to simplify the implementation of register + // renaming. We find the architectural register index by indexing + // into the instruction's own operand index table. Note that a + // raw pointer to the StaticInst is provided instead of a + // ref-counted StaticInstPtr to redice overhead. This is fine as + // long as these methods don't copy the pointer into any long-term + // storage (which is pretty hard to imagine they would have reason + // to do). + + uint64_t readIntRegOperand(const StaticInst *si, int idx) + { + return this->cpu->readIntReg(this->_srcRegIdx[idx]); + } + + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) + { + return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); + } + + FloatReg readFloatRegOperand(const StaticInst *si, int idx) + { + return this->cpu->readFloatReg(this->_srcRegIdx[idx]); + } + + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) + { + return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); + } + + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) + { + return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); + } + + /** @todo: Make results into arrays so they can handle multiple dest + * registers. + */ + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) + { + this->cpu->setIntReg(this->_destRegIdx[idx], val); + BaseDynInst<Impl>::setIntRegOperand(si, idx, val); + } + + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) + { + this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); + } + + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) + { + this->cpu->setFloatReg(this->_destRegIdx[idx], val); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); + } + + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) + { + this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); + } + + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) + { + this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); + } + +#if THE_ISA == MIPS_ISA + uint64_t readRegOtherThread(int misc_reg) + { + panic("MIPS MT not defined for O3 CPU.\n"); + return 0; + } + + void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) + { + panic("MIPS MT not defined for O3 CPU.\n"); + } +#endif + + public: + /** Calculates EA part of a memory instruction. Currently unused, + * though it may be useful in the future if we want to split + * memory operations into EA calculation and memory access parts. + */ + Fault calcEA() + { + return this->staticInst->eaCompInst()->execute(this, this->traceData); + } + + /** Does the memory access part of a memory instruction. Currently unused, + * though it may be useful in the future if we want to split + * memory operations into EA calculation and memory access parts. + */ + Fault memAccess() + { + return this->staticInst->memAccInst()->execute(this, this->traceData); + } +}; + +#endif // __CPU_O3_ALPHA_DYN_INST_HH__ + diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh index 6dfe0ccdd..8d391ceaf 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/dyn_inst_impl.hh @@ -28,34 +28,35 @@ * Authors: Kevin Lim */ -#include "cpu/o3/alpha/dyn_inst.hh" +#include "base/cp_annotate.hh" +#include "cpu/o3/dyn_inst.hh" template <class Impl> -AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr staticInst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, - Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) +BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, + Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, + Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu) : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) + Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) { initVars(); } template <class Impl> -AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, - Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) +BaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, + Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, + Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu) : BaseDynInst<Impl>(inst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) + Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) { initVars(); } template <class Impl> -AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst) +BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) : BaseDynInst<Impl>(_staticInst) { initVars(); @@ -63,7 +64,7 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst) template <class Impl> void -AlphaDynInst<Impl>::initVars() +BaseO3DynInst<Impl>::initVars() { // Make sure to have the renamed register entries set to the same // as the normal register entries. It will allow the IQ to work @@ -80,7 +81,7 @@ AlphaDynInst<Impl>::initVars() template <class Impl> Fault -AlphaDynInst<Impl>::execute() +BaseO3DynInst<Impl>::execute() { // @todo: Pretty convoluted way to avoid squashing from happening // when using the TC during an instruction's execution @@ -98,7 +99,7 @@ AlphaDynInst<Impl>::execute() template <class Impl> Fault -AlphaDynInst<Impl>::initiateAcc() +BaseO3DynInst<Impl>::initiateAcc() { // @todo: Pretty convoluted way to avoid squashing from happening // when using the TC during an instruction's execution @@ -116,7 +117,7 @@ AlphaDynInst<Impl>::initiateAcc() template <class Impl> Fault -AlphaDynInst<Impl>::completeAcc(PacketPtr pkt) +BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) { this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); @@ -126,8 +127,9 @@ AlphaDynInst<Impl>::completeAcc(PacketPtr pkt) #if FULL_SYSTEM template <class Impl> Fault -AlphaDynInst<Impl>::hwrei() +BaseO3DynInst<Impl>::hwrei() { +#if THE_ISA == ALPHA_ISA // Can only do a hwrei when in pal mode. if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; @@ -135,33 +137,50 @@ AlphaDynInst<Impl>::hwrei() // Set the next PC based on the value of the EXC_ADDR IPR. this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, this->threadNumber)); + if (CPA::available()) { + ThreadContext *tc = this->cpu->tcBase(this->threadNumber); + CPA::cpa()->swAutoBegin(tc, this->readNextPC()); + } // Tell CPU to clear any state it needs to if a hwrei is taken. this->cpu->hwrei(this->threadNumber); +#else +#endif // FIXME: XXX check for interrupts? XXX return NoFault; } template <class Impl> void -AlphaDynInst<Impl>::trap(Fault fault) +BaseO3DynInst<Impl>::trap(Fault fault) { this->cpu->trap(fault, this->threadNumber); } template <class Impl> bool -AlphaDynInst<Impl>::simPalCheck(int palFunc) +BaseO3DynInst<Impl>::simPalCheck(int palFunc) { +#if THE_ISA != ALPHA_ISA + panic("simPalCheck called, but PAL only exists in Alpha!\n"); +#endif return this->cpu->simPalCheck(palFunc, this->threadNumber); } #else template <class Impl> void -AlphaDynInst<Impl>::syscall(int64_t callnum) +BaseO3DynInst<Impl>::syscall(int64_t callnum) { + // HACK: check CPU's nextPC before and after syscall. If it + // changes, update this instruction's nextPC because the syscall + // must have changed the nextPC. + Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber); this->cpu->syscall(callnum, this->threadNumber); + Addr new_next_pc = this->cpu->readNextPC(this->threadNumber); + if (cpu_next_pc != new_next_pc) { + this->setNextPC(new_next_pc); + } } #endif diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index d954bd1e7..08ccb094b 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -41,6 +41,8 @@ #include "mem/port.hh" #include "sim/eventq.hh" +class DerivO3CPUParams; + /** * DefaultFetch class handles both single threaded and SMT fetch. Its * width is specified by the parameters; each cycle it tries to fetch @@ -58,7 +60,6 @@ class DefaultFetch typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; - typedef typename Impl::Params Params; /** Typedefs from the CPU policy. */ typedef typename CPUPol::BPredUnit BPredUnit; @@ -81,7 +82,7 @@ class DefaultFetch public: /** Default constructor. */ IcachePort(DefaultFetch<Impl> *_fetch) - : Port(_fetch->name() + "-iport"), fetch(_fetch) + : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) { } bool snoopRangeSent; @@ -160,7 +161,7 @@ class DefaultFetch public: /** DefaultFetch constructor. */ - DefaultFetch(O3CPU *_cpu, Params *params); + DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); /** Returns the name of fetch. */ std::string name() const; @@ -447,33 +448,33 @@ class DefaultFetch // @todo: Consider making these vectors and tracking on a per thread basis. /** Stat for total number of cycles stalled due to an icache miss. */ - Stats::Scalar<> icacheStallCycles; + Stats::Scalar icacheStallCycles; /** Stat for total number of fetched instructions. */ - Stats::Scalar<> fetchedInsts; + Stats::Scalar fetchedInsts; /** Total number of fetched branches. */ - Stats::Scalar<> fetchedBranches; + Stats::Scalar fetchedBranches; /** Stat for total number of predicted branches. */ - Stats::Scalar<> predictedBranches; + Stats::Scalar predictedBranches; /** Stat for total number of cycles spent fetching. */ - Stats::Scalar<> fetchCycles; + Stats::Scalar fetchCycles; /** Stat for total number of cycles spent squashing. */ - Stats::Scalar<> fetchSquashCycles; + Stats::Scalar fetchSquashCycles; /** Stat for total number of cycles spent blocked due to other stages in * the pipeline. */ - Stats::Scalar<> fetchIdleCycles; + Stats::Scalar fetchIdleCycles; /** Total number of cycles spent blocked. */ - Stats::Scalar<> fetchBlockedCycles; + Stats::Scalar fetchBlockedCycles; /** Total number of cycles spent in any other state. */ - Stats::Scalar<> fetchMiscStallCycles; + Stats::Scalar fetchMiscStallCycles; /** Stat for total number of fetched cache lines. */ - Stats::Scalar<> fetchedCacheLines; + Stats::Scalar fetchedCacheLines; /** Total number of outstanding icache accesses that were dropped * due to a squash. */ - Stats::Scalar<> fetchIcacheSquashes; + Stats::Scalar fetchIcacheSquashes; /** Distribution of number of instructions fetched each cycle. */ - Stats::Distribution<> fetchNisnDist; + Stats::Distribution fetchNisnDist; /** Rate of how often fetch was idle. */ Stats::Formula idleRate; /** Number of branch fetches per cycle. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 7d344fa33..79a4f2b7a 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -51,6 +51,8 @@ #include "sim/system.hh" #endif // FULL_SYSTEM +#include "params/DerivO3CPU.hh" + template<class Impl> void DefaultFetch<Impl>::IcachePort::setPeer(Port *port) @@ -111,7 +113,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry() } template<class Impl> -DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params) +DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) : cpu(_cpu), branchPred(params), predecoder(NULL), @@ -123,14 +125,16 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params) cacheBlocked(false), retryPkt(NULL), retryTid(-1), - numThreads(params->numberOfThreads), + numThreads(params->numThreads), numFetchingThreads(params->smtNumFetchingThreads), interruptPending(false), drainPending(false), switchedOut(false) { if (numThreads > Impl::MaxThreads) - fatal("numThreads is not a valid value\n"); + fatal("numThreads (%d) is larger than compiled limit (%d),\n" + "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", + numThreads, static_cast<int>(Impl::MaxThreads)); // Set fetch stage's status to inactive. _status = Inactive; @@ -360,7 +364,7 @@ template<class Impl> void DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) { - unsigned tid = pkt->req->getThreadNum(); + unsigned tid = pkt->req->threadId(); DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); @@ -591,12 +595,13 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Set the appropriate read size and flags as well. // Build request here. RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, - fetch_PC, cpu->readCpuId(), tid); + fetch_PC, cpu->thread[tid]->contextId(), + tid); memReq[tid] = mem_req; // Translate the instruction request. - fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); + fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC()); // In the case of faults, the fetch stage may need to stall and wait // for the ITB miss to be handled. diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 457e2a024..3458f09d6 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -41,6 +41,7 @@ #include "cpu/o3/scoreboard.hh" #include "cpu/o3/lsq.hh" +class DerivO3CPUParams; class FUPool; /** @@ -70,7 +71,6 @@ class DefaultIEW typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; - typedef typename Impl::Params Params; typedef typename CPUPol::IQ IQ; typedef typename CPUPol::RenameMap RenameMap; @@ -115,7 +115,7 @@ class DefaultIEW public: /** Constructs a DefaultIEW with the given parameters. */ - DefaultIEW(O3CPU *_cpu, Params *params); + DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); /** Returns the name of the DefaultIEW stage. */ std::string name() const; @@ -208,6 +208,9 @@ class DefaultIEW /** Returns if the LSQ has any stores to writeback. */ bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } + /** Returns if the LSQ has any stores to writeback. */ + bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); } + void incrWb(InstSeqNum &sn) { if (++wbOutstanding == wbMax) @@ -462,69 +465,69 @@ class DefaultIEW bool switchedOut; /** Stat for total number of idle cycles. */ - Stats::Scalar<> iewIdleCycles; + Stats::Scalar iewIdleCycles; /** Stat for total number of squashing cycles. */ - Stats::Scalar<> iewSquashCycles; + Stats::Scalar iewSquashCycles; /** Stat for total number of blocking cycles. */ - Stats::Scalar<> iewBlockCycles; + Stats::Scalar iewBlockCycles; /** Stat for total number of unblocking cycles. */ - Stats::Scalar<> iewUnblockCycles; + Stats::Scalar iewUnblockCycles; /** Stat for total number of instructions dispatched. */ - Stats::Scalar<> iewDispatchedInsts; + Stats::Scalar iewDispatchedInsts; /** Stat for total number of squashed instructions dispatch skips. */ - Stats::Scalar<> iewDispSquashedInsts; + Stats::Scalar iewDispSquashedInsts; /** Stat for total number of dispatched load instructions. */ - Stats::Scalar<> iewDispLoadInsts; + Stats::Scalar iewDispLoadInsts; /** Stat for total number of dispatched store instructions. */ - Stats::Scalar<> iewDispStoreInsts; + Stats::Scalar iewDispStoreInsts; /** Stat for total number of dispatched non speculative instructions. */ - Stats::Scalar<> iewDispNonSpecInsts; + Stats::Scalar iewDispNonSpecInsts; /** Stat for number of times the IQ becomes full. */ - Stats::Scalar<> iewIQFullEvents; + Stats::Scalar iewIQFullEvents; /** Stat for number of times the LSQ becomes full. */ - Stats::Scalar<> iewLSQFullEvents; + Stats::Scalar iewLSQFullEvents; /** Stat for total number of memory ordering violation events. */ - Stats::Scalar<> memOrderViolationEvents; + Stats::Scalar memOrderViolationEvents; /** Stat for total number of incorrect predicted taken branches. */ - Stats::Scalar<> predictedTakenIncorrect; + Stats::Scalar predictedTakenIncorrect; /** Stat for total number of incorrect predicted not taken branches. */ - Stats::Scalar<> predictedNotTakenIncorrect; + Stats::Scalar predictedNotTakenIncorrect; /** Stat for total number of mispredicted branches detected at execute. */ Stats::Formula branchMispredicts; /** Stat for total number of executed instructions. */ - Stats::Scalar<> iewExecutedInsts; + Stats::Scalar iewExecutedInsts; /** Stat for total number of executed load instructions. */ - Stats::Vector<> iewExecLoadInsts; + Stats::Vector iewExecLoadInsts; /** Stat for total number of executed store instructions. */ -// Stats::Scalar<> iewExecStoreInsts; +// Stats::Scalar iewExecStoreInsts; /** Stat for total number of squashed instructions skipped at execute. */ - Stats::Scalar<> iewExecSquashedInsts; + Stats::Scalar iewExecSquashedInsts; /** Number of executed software prefetches. */ - Stats::Vector<> iewExecutedSwp; + Stats::Vector iewExecutedSwp; /** Number of executed nops. */ - Stats::Vector<> iewExecutedNop; + Stats::Vector iewExecutedNop; /** Number of executed meomory references. */ - Stats::Vector<> iewExecutedRefs; + Stats::Vector iewExecutedRefs; /** Number of executed branches. */ - Stats::Vector<> iewExecutedBranches; + Stats::Vector iewExecutedBranches; /** Number of executed store instructions. */ Stats::Formula iewExecStoreInsts; /** Number of instructions executed per cycle. */ Stats::Formula iewExecRate; /** Number of instructions sent to commit. */ - Stats::Vector<> iewInstsToCommit; + Stats::Vector iewInstsToCommit; /** Number of instructions that writeback. */ - Stats::Vector<> writebackCount; + Stats::Vector writebackCount; /** Number of instructions that wake consumers. */ - Stats::Vector<> producerInst; + Stats::Vector producerInst; /** Number of instructions that wake up from producers. */ - Stats::Vector<> consumerInst; + Stats::Vector consumerInst; /** Number of instructions that were delayed in writing back due * to resource contention. */ - Stats::Vector<> wbPenalized; + Stats::Vector wbPenalized; /** Number of instructions per cycle written back. */ Stats::Formula wbRate; /** Average number of woken instructions per writeback. */ diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 84d10e966..1daecd669 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -37,9 +37,10 @@ #include "base/timebuf.hh" #include "cpu/o3/fu_pool.hh" #include "cpu/o3/iew.hh" +#include "params/DerivO3CPU.hh" template<class Impl> -DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params) +DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) : issueToExecQueue(params->backComSize, params->forwardComSize), cpu(_cpu), instQueue(_cpu, this, params), @@ -52,7 +53,7 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params) issueWidth(params->issueWidth), wbOutstanding(0), wbWidth(params->wbWidth), - numThreads(params->numberOfThreads), + numThreads(params->numThreads), switchedOut(false) { _status = Active; diff --git a/src/cpu/o3/sparc/impl.hh b/src/cpu/o3/impl.hh index 0a970c2f0..4b29b4daa 100644 --- a/src/cpu/o3/sparc/impl.hh +++ b/src/cpu/o3/impl.hh @@ -25,24 +25,23 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Gabe Black + * Authors: Kevin Lim */ -#ifndef __CPU_O3_SPARC_IMPL_HH__ -#define __CPU_O3_SPARC_IMPL_HH__ +#ifndef __CPU_O3_IMPL_HH__ +#define __CPU_O3_IMPL_HH__ -#include "arch/sparc/isa_traits.hh" +#include "arch/isa_traits.hh" -#include "cpu/o3/sparc/params.hh" #include "cpu/o3/cpu_policy.hh" // Forward declarations. template <class Impl> -class SparcDynInst; +class BaseO3DynInst; template <class Impl> -class SparcO3CPU; +class FullO3CPU; /** Implementation specific struct that defines several key types to the * CPU, the stages within the CPU, the time buffers, and the DynInst. @@ -52,16 +51,16 @@ class SparcO3CPU; * This is one of the key things that must be defined for each hardware * specific CPU implementation. */ -struct SparcSimpleImpl +struct O3CPUImpl { /** The type of MachInst. */ typedef TheISA::MachInst MachInst; /** The CPU policy to be used, which defines all of the CPU stages. */ - typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol; + typedef SimpleCPUPolicy<O3CPUImpl> CPUPol; /** The DynInst type to be used. */ - typedef SparcDynInst<SparcSimpleImpl> DynInst; + typedef BaseO3DynInst<O3CPUImpl> DynInst; /** The refcounted DynInst pointer to be used. In most cases this is * what should be used, and not DynInst *. @@ -69,7 +68,7 @@ struct SparcSimpleImpl typedef RefCountingPtr<DynInst> DynInstPtr; /** The O3CPU type to be used. */ - typedef SparcO3CPU<SparcSimpleImpl> O3CPU; + typedef FullO3CPU<O3CPUImpl> O3CPU; /** Same typedef, but for CPUType. BaseDynInst may not always use * an O3 CPU, so it's clearer to call it CPUType instead in that @@ -77,16 +76,10 @@ struct SparcSimpleImpl */ typedef O3CPU CPUType; - /** The Params to be passed to each stage. */ - typedef SparcSimpleParams Params; - enum { MaxWidth = 8, MaxThreads = 4 }; }; -/** The O3Impl to be used. */ -typedef SparcSimpleImpl O3CPUImpl; - #endif // __CPU_O3_SPARC_IMPL_HH__ diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index d0f503977..0c3f44436 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -41,8 +41,10 @@ #include "cpu/inst_seq.hh" #include "cpu/o3/dep_graph.hh" #include "cpu/op_class.hh" +#include "sim/eventq.hh" #include "sim/host.hh" +class DerivO3CPUParams; class FUPool; class MemInterface; @@ -70,7 +72,6 @@ class InstructionQueue //Typedefs from the Impl. typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::Params Params; typedef typename Impl::CPUPol::IEW IEW; typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; @@ -110,7 +111,7 @@ class InstructionQueue }; /** Constructs an IQ. */ - InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params); + InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); /** Destructs the IQ. */ ~InstructionQueue(); @@ -442,58 +443,58 @@ class InstructionQueue void dumpInsts(); /** Stat for number of instructions added. */ - Stats::Scalar<> iqInstsAdded; + Stats::Scalar iqInstsAdded; /** Stat for number of non-speculative instructions added. */ - Stats::Scalar<> iqNonSpecInstsAdded; + Stats::Scalar iqNonSpecInstsAdded; - Stats::Scalar<> iqInstsIssued; + Stats::Scalar iqInstsIssued; /** Stat for number of integer instructions issued. */ - Stats::Scalar<> iqIntInstsIssued; + Stats::Scalar iqIntInstsIssued; /** Stat for number of floating point instructions issued. */ - Stats::Scalar<> iqFloatInstsIssued; + Stats::Scalar iqFloatInstsIssued; /** Stat for number of branch instructions issued. */ - Stats::Scalar<> iqBranchInstsIssued; + Stats::Scalar iqBranchInstsIssued; /** Stat for number of memory instructions issued. */ - Stats::Scalar<> iqMemInstsIssued; + Stats::Scalar iqMemInstsIssued; /** Stat for number of miscellaneous instructions issued. */ - Stats::Scalar<> iqMiscInstsIssued; + Stats::Scalar iqMiscInstsIssued; /** Stat for number of squashed instructions that were ready to issue. */ - Stats::Scalar<> iqSquashedInstsIssued; + Stats::Scalar iqSquashedInstsIssued; /** Stat for number of squashed instructions examined when squashing. */ - Stats::Scalar<> iqSquashedInstsExamined; + Stats::Scalar iqSquashedInstsExamined; /** Stat for number of squashed instruction operands examined when * squashing. */ - Stats::Scalar<> iqSquashedOperandsExamined; + Stats::Scalar iqSquashedOperandsExamined; /** Stat for number of non-speculative instructions removed due to a squash. */ - Stats::Scalar<> iqSquashedNonSpecRemoved; + Stats::Scalar iqSquashedNonSpecRemoved; // Also include number of instructions rescheduled and replayed. /** Distribution of number of instructions in the queue. * @todo: Need to create struct to track the entry time for each * instruction. */ -// Stats::VectorDistribution<> queueResDist; +// Stats::VectorDistribution queueResDist; /** Distribution of the number of instructions issued. */ - Stats::Distribution<> numIssuedDist; + Stats::Distribution numIssuedDist; /** Distribution of the cycles it takes to issue an instruction. * @todo: Need to create struct to track the ready time for each * instruction. */ -// Stats::VectorDistribution<> issueDelayDist; +// Stats::VectorDistribution issueDelayDist; /** Number of times an instruction could not be issued because a * FU was busy. */ - Stats::Vector<> statFuBusy; -// Stats::Vector<> dist_unissued; + Stats::Vector statFuBusy; +// Stats::Vector dist_unissued; /** Stat for total number issued for each instruction type. */ - Stats::Vector2d<> statIssuedInstType; + Stats::Vector2d statIssuedInstType; /** Number of instructions issued per cycle. */ Stats::Formula issueRate; /** Number of times the FU was busy. */ - Stats::Vector<> fuBusy; + Stats::Vector fuBusy; /** Number of times the FU was busy per instruction issued. */ Stats::Formula fuBusyRate; }; diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index fb06f20df..1d0f4b9f6 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -37,12 +37,13 @@ #include "enums/OpClass.hh" #include "sim/core.hh" +#include "params/DerivO3CPU.hh" + template <class Impl> InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, - int fu_idx, - InstructionQueue<Impl> *iq_ptr) - : Event(&mainEventQueue, Stat_Event_Pri), - inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) + int fu_idx, InstructionQueue<Impl> *iq_ptr) + : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), + freeFU(false) { this->setFlags(Event::AutoDelete); } @@ -65,7 +66,7 @@ InstructionQueue<Impl>::FUCompletion::description() const template <class Impl> InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, - Params *params) + DerivO3CPUParams *params) : cpu(cpu_ptr), iewStage(iew_ptr), fuPool(params->fuPool), @@ -79,7 +80,7 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, switchedOut = false; - numThreads = params->numberOfThreads; + numThreads = params->numThreads; // Set the number of physical registers as the number of int + float numPhysRegs = numPhysIntRegs + numPhysFloatRegs; @@ -752,7 +753,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() FUCompletion *execution = new FUCompletion(issuing_inst, idx, this); - execution->schedule(curTick + cpu->ticks(op_latency - 1)); + cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1)); // @todo: Enforce that issue_latency == 1 or op_latency if (issue_latency > 1) { diff --git a/src/cpu/o3/isa_specific.hh b/src/cpu/o3/isa_specific.hh index 72a8d4021..e9347af91 100755 --- a/src/cpu/o3/isa_specific.hh +++ b/src/cpu/o3/isa_specific.hh @@ -30,21 +30,5 @@ #include "cpu/base.hh" -#if THE_ISA == ALPHA_ISA - #include "cpu/o3/alpha/cpu.hh" - #include "cpu/o3/alpha/impl.hh" - #include "cpu/o3/alpha/params.hh" - #include "cpu/o3/alpha/dyn_inst.hh" -#elif THE_ISA == MIPS_ISA - #include "cpu/o3/mips/cpu.hh" - #include "cpu/o3/mips/impl.hh" - #include "cpu/o3/mips/params.hh" - #include "cpu/o3/mips/dyn_inst.hh" -#elif THE_ISA == SPARC_ISA - #include "cpu/o3/sparc/cpu.hh" - #include "cpu/o3/sparc/impl.hh" - #include "cpu/o3/sparc/params.hh" - #include "cpu/o3/sparc/dyn_inst.hh" -#else - #error "ISA-specific header files O3CPU not defined ISA" -#endif +#include "cpu/o3/impl.hh" +#include "cpu/o3/dyn_inst.hh" diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 06de608e0..cf27552d4 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -40,10 +40,11 @@ #include "mem/port.hh" #include "sim/sim_object.hh" +class DerivO3CPUParams; + template <class Impl> class LSQ { public: - typedef typename Impl::Params Params; typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::CPUPol::IEW IEW; @@ -57,7 +58,7 @@ class LSQ { }; /** Constructs an LSQ with the given parameters. */ - LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params); + LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); /** Returns the name of the LSQ. */ std::string name() const; @@ -297,7 +298,7 @@ class LSQ { public: /** Default constructor. */ DcachePort(LSQ *_lsq) - : Port(_lsq->name() + "-dport"), lsq(_lsq) + : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq) { } bool snoopRangeSent; @@ -370,7 +371,7 @@ template <class T> Fault LSQ<Impl>::read(RequestPtr req, T &data, int load_idx) { - unsigned tid = req->getThreadNum(); + unsigned tid = req->threadId(); return thread[tid].read(req, data, load_idx); } @@ -380,7 +381,7 @@ template <class T> Fault LSQ<Impl>::write(RequestPtr req, T &data, int store_idx) { - unsigned tid = req->getThreadNum(); + unsigned tid = req->threadId(); return thread[tid].write(req, data, store_idx); } diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 8ed6f7f54..8f9f63081 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -34,6 +34,8 @@ #include "cpu/o3/lsq.hh" +#include "params/DerivO3CPU.hh" + template<class Impl> void LSQ<Impl>::DcachePort::setPeer(Port *port) @@ -83,7 +85,7 @@ LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) if (pkt->isError()) DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr()); if (pkt->isResponse()) { - lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); + lsq->thread[pkt->req->threadId()].completeDataAccess(pkt); } else { // must be a snoop @@ -111,11 +113,11 @@ LSQ<Impl>::DcachePort::recvRetry() } template <class Impl> -LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params) +LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this), LQEntries(params->LQEntries), SQEntries(params->SQEntries), - numThreads(params->numberOfThreads), + numThreads(params->numThreads), retryTid(-1) { dcachePort.snoopRangeSent = false; @@ -582,17 +584,14 @@ LSQ<Impl>::hasStoresToWB() std::list<unsigned>::iterator threads = activeThreads->begin(); std::list<unsigned>::iterator end = activeThreads->end(); - if (threads == end) - return false; - while (threads != end) { unsigned tid = *threads++; - if (!hasStoresToWB(tid)) - return false; + if (hasStoresToWB(tid)) + return true; } - return true; + return false; } template<class Impl> @@ -605,11 +604,11 @@ LSQ<Impl>::willWB() while (threads != end) { unsigned tid = *threads++; - if (!willWB(tid)) - return false; + if (willWB(tid)) + return true; } - return true; + return false; } template<class Impl> diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 128a71dbc..5323e3a47 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -40,11 +40,14 @@ #include "arch/faults.hh" #include "arch/locked_mem.hh" #include "config/full_system.hh" +#include "base/fast_alloc.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" #include "mem/packet.hh" #include "mem/port.hh" +class DerivO3CPUParams; + /** * Class that implements the actual LQ and SQ for each specific * thread. Both are circular queues; load entries are freed upon @@ -62,7 +65,6 @@ class LSQUnit { protected: typedef TheISA::IntReg IntReg; public: - typedef typename Impl::Params Params; typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::CPUPol::IEW IEW; @@ -74,8 +76,9 @@ class LSQUnit { LSQUnit(); /** Initializes the LSQ unit with the specified number of entries. */ - void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr, - unsigned maxLQEntries, unsigned maxSQEntries, unsigned id); + void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, + LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, + unsigned id); /** Returns the name of the LSQ unit. */ std::string name() const; @@ -245,7 +248,7 @@ class LSQUnit { Port *dcachePort; /** Derived class to hold any sender state the LSQ needs. */ - class LSQSenderState : public Packet::SenderState + class LSQSenderState : public Packet::SenderState, public FastAlloc { public: /** Default constructor. */ @@ -406,35 +409,35 @@ class LSQUnit { // of that in stage that is one level up, and only call executeLoad/Store // the appropriate number of times. /** Total number of loads forwaded from LSQ stores. */ - Stats::Scalar<> lsqForwLoads; + Stats::Scalar lsqForwLoads; /** Total number of loads ignored due to invalid addresses. */ - Stats::Scalar<> invAddrLoads; + Stats::Scalar invAddrLoads; /** Total number of squashed loads. */ - Stats::Scalar<> lsqSquashedLoads; + Stats::Scalar lsqSquashedLoads; /** Total number of responses from the memory system that are * ignored due to the instruction already being squashed. */ - Stats::Scalar<> lsqIgnoredResponses; + Stats::Scalar lsqIgnoredResponses; /** Tota number of memory ordering violations. */ - Stats::Scalar<> lsqMemOrderViolation; + Stats::Scalar lsqMemOrderViolation; /** Total number of squashed stores. */ - Stats::Scalar<> lsqSquashedStores; + Stats::Scalar lsqSquashedStores; /** Total number of software prefetches ignored due to invalid addresses. */ - Stats::Scalar<> invAddrSwpfs; + Stats::Scalar invAddrSwpfs; /** Ready loads blocked due to partial store-forwarding. */ - Stats::Scalar<> lsqBlockedLoads; + Stats::Scalar lsqBlockedLoads; /** Number of loads that were rescheduled. */ - Stats::Scalar<> lsqRescheduledLoads; + Stats::Scalar lsqRescheduledLoads; /** Number of times the LSQ is blocked due to the cache. */ - Stats::Scalar<> lsqCacheBlocked; + Stats::Scalar lsqCacheBlocked; public: /** Executes the load at the given index. */ @@ -581,7 +584,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) // We'll say this has a 1 cycle load-store forwarding latency // for now. // @todo: Need to make this a parameter. - wb->schedule(curTick); + cpu->schedule(wb, curTick); ++lsqForwLoads; return NoFault; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index e6ff5e931..85662d496 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -45,7 +45,7 @@ template<class Impl> LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, LSQUnit *lsq_ptr) - : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) + : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) { this->setFlags(Event::AutoDelete); } @@ -112,8 +112,9 @@ LSQUnit<Impl>::LSQUnit() template<class Impl> void -LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr, - unsigned maxLQEntries, unsigned maxSQEntries, unsigned id) +LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, + LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, + unsigned id) { cpu = cpu_ptr; iewStage = iew_ptr; @@ -683,7 +684,7 @@ LSQUnit<Impl>::writebackStores() "Instantly completing it.\n", inst->seqNum); WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); - wb->schedule(curTick + 1); + cpu->schedule(wb, curTick + 1); completeStore(storeWBIdx); incrStIdx(storeWBIdx); continue; diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index a12a3001b..4f9e7c9f7 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -48,6 +48,8 @@ struct SNHash { } }; +class DerivO3CPUParams; + template <class Impl> class InstructionQueue; @@ -63,25 +65,28 @@ class InstructionQueue; * dependence prediction schemes. */ template <class MemDepPred, class Impl> -class MemDepUnit { +class MemDepUnit +{ + protected: + std::string _name; + public: - typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; /** Empty constructor. Must call init() prior to using in this case. */ MemDepUnit(); /** Constructs a MemDepUnit with given parameters. */ - MemDepUnit(Params *params); + MemDepUnit(DerivO3CPUParams *params); /** Frees up any memory allocated. */ ~MemDepUnit(); /** Returns the name of the memory dependence unit. */ - std::string name() const; + std::string name() const { return _name; } /** Initializes the unit with parameters and a thread id. */ - void init(Params *params, int tid); + void init(DerivO3CPUParams *params, int tid); /** Registers statistics. */ void regStats(); @@ -252,13 +257,13 @@ class MemDepUnit { int id; /** Stat for number of inserted loads. */ - Stats::Scalar<> insertedLoads; + Stats::Scalar insertedLoads; /** Stat for number of inserted stores. */ - Stats::Scalar<> insertedStores; + Stats::Scalar insertedStores; /** Stat for number of conflicting loads that had to wait for a store. */ - Stats::Scalar<> conflictingLoads; + Stats::Scalar conflictingLoads; /** Stat for number of conflicting stores that had to wait for a store. */ - Stats::Scalar<> conflictingStores; + Stats::Scalar conflictingStores; }; #endif // __CPU_O3_MEM_DEP_UNIT_HH__ diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh index 64558efaa..8754539f9 100644 --- a/src/cpu/o3/mem_dep_unit_impl.hh +++ b/src/cpu/o3/mem_dep_unit_impl.hh @@ -33,6 +33,8 @@ #include "cpu/o3/inst_queue.hh" #include "cpu/o3/mem_dep_unit.hh" +#include "params/DerivO3CPU.hh" + template <class MemDepPred, class Impl> MemDepUnit<MemDepPred, Impl>::MemDepUnit() : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), @@ -41,8 +43,9 @@ MemDepUnit<MemDepPred, Impl>::MemDepUnit() } template <class MemDepPred, class Impl> -MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) - : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), +MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) + : _name(params->name + ".memdepunit"), + depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) { DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); @@ -74,18 +77,12 @@ MemDepUnit<MemDepPred, Impl>::~MemDepUnit() } template <class MemDepPred, class Impl> -std::string -MemDepUnit<MemDepPred, Impl>::name() const -{ - return "memdepunit"; -} - -template <class MemDepPred, class Impl> void -MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid) +MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid) { DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); + _name = csprintf("%s.memDep%d", params->name, tid); id = tid; depPred.init(params->SSITSize, params->LFSTSize); @@ -96,19 +93,19 @@ void MemDepUnit<MemDepPred, Impl>::regStats() { insertedLoads - .name(name() + ".memDep.insertedLoads") + .name(name() + ".insertedLoads") .desc("Number of loads inserted to the mem dependence unit."); insertedStores - .name(name() + ".memDep.insertedStores") + .name(name() + ".insertedStores") .desc("Number of stores inserted to the mem dependence unit."); conflictingLoads - .name(name() + ".memDep.conflictingLoads") + .name(name() + ".conflictingLoads") .desc("Number of conflicting loads."); conflictingStores - .name(name() + ".memDep.conflictingStores") + .name(name() + ".conflictingStores") .desc("Number of conflicting stores."); } diff --git a/src/cpu/o3/mips/cpu.cc b/src/cpu/o3/mips/cpu.cc deleted file mode 100755 index 420f460b2..000000000 --- a/src/cpu/o3/mips/cpu.cc +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include "cpu/o3/mips/impl.hh" -#include "cpu/o3/mips/cpu_impl.hh" -#include "cpu/o3/mips/dyn_inst.hh" - -// Force instantiation of MipsO3CPU for all the implemntations that are -// needed. Consider merging this and mips_dyn_inst.cc, and maybe all -// classes that depend on a certain impl, into one file (mips_impl.cc?). -template class MipsO3CPU<MipsSimpleImpl>; diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh deleted file mode 100755 index 3724ced46..000000000 --- a/src/cpu/o3/mips/cpu.hh +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#ifndef __CPU_O3_MIPS_CPU_HH__ -#define __CPU_O3_MIPS_CPU_HH__ - -#include "arch/mips/regfile.hh" -#include "arch/mips/syscallreturn.hh" -#include "cpu/thread_context.hh" -#include "cpu/o3/cpu.hh" -#include "sim/byteswap.hh" -#include "sim/faults.hh" - -class EndQuiesceEvent; -namespace Kernel { - class Statistics; -}; - -class TranslatingPort; - -/** - * MipsO3CPU class. Derives from the FullO3CPU class, and - * implements all ISA and implementation specific functions of the - * CPU. This is the CPU class that is used for the SimObjects, and is - * what is given to the DynInsts. Most of its state exists in the - * FullO3CPU; the state is has is mainly for ISA specific - * functionality. - */ -template <class Impl> -class MipsO3CPU : public FullO3CPU<Impl> -{ - public: - typedef O3ThreadState<Impl> ImplState; - typedef O3ThreadState<Impl> Thread; - typedef typename Impl::Params Params; - - /** Constructs an MipsO3CPU with the given parameters. */ - MipsO3CPU(Params *params); - - /** Registers statistics. */ - void regStats(); - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); - - /** Reads a misc. register, including any side effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); - - /** Sets a miscellaneous register. */ - void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); - - /** Sets a misc. register, including any side effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, - const TheISA::MiscReg &val, unsigned tid); - - /** Initiates a squash of all in-flight instructions for a given - * thread. The source of the squash is an external update of - * state through the TC. - */ - void squashFromTC(unsigned tid); - - /** Traps to handle given fault. */ - void trap(Fault fault, unsigned tid); - - /** Executes a syscall. - * @todo: Determine if this needs to be virtual. - */ - void syscall(int64_t callnum, int tid); - /** Gets a syscall argument. */ - TheISA::IntReg getSyscallArg(int i, int tid); - - /** Used to shift args for indirect syscall. */ - void setSyscallArg(int i, TheISA::IntReg val, int tid); - - /** Sets the return value of a syscall. */ - void setSyscallReturn(SyscallReturn return_value, int tid); - - /** CPU read function, forwards read to LSQ. */ - template <class T> - Fault read(RequestPtr &req, T &data, int load_idx) - { - return this->iew.ldstQueue.read(req, data, load_idx); - } - - /** CPU write function, forwards write to LSQ. */ - template <class T> - Fault write(RequestPtr &req, T &data, int store_idx) - { - return this->iew.ldstQueue.write(req, data, store_idx); - } - - Addr lockAddr; - - /** Temporary fix for the lock flag, works in the UP case. */ - bool lockFlag; -}; - -#endif // __CPU_O3_MIPS_CPU_HH__ diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc deleted file mode 100644 index 4690b9804..000000000 --- a/src/cpu/o3/mips/cpu_builder.cc +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include <string> - -#include "config/use_checker.hh" -#include "cpu/base.hh" -#include "cpu/o3/mips/cpu.hh" -#include "cpu/o3/mips/impl.hh" -#include "cpu/o3/mips/params.hh" -#include "cpu/o3/fu_pool.hh" -#include "params/DerivO3CPU.hh" - -class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl> -{ - public: - DerivO3CPU(MipsSimpleParams *p) - : MipsO3CPU<MipsSimpleImpl>(p) - { } -}; - -DerivO3CPU * -DerivO3CPUParams::create() -{ - DerivO3CPU *cpu; - - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - int actual_num_threads = - (numThreads >= workload.size()) ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); - } - - MipsSimpleParams *params = new MipsSimpleParams; - - params->clock = clock; - params->phase = phase; - - params->tracer = tracer; - - params->name = name; - params->numberOfThreads = actual_num_threads; - params->cpu_id = cpu_id; - params->activity = activity; - - params->workload = workload; - -#if USE_CHECKER - params->checker = checker; -#endif - - params->max_insts_any_thread = max_insts_any_thread; - params->max_insts_all_threads = max_insts_all_threads; - params->max_loads_any_thread = max_loads_any_thread; - params->max_loads_all_threads = max_loads_all_threads; - - // - // Caches - // - params->cachePorts = cachePorts; - - params->decodeToFetchDelay = decodeToFetchDelay; - params->renameToFetchDelay = renameToFetchDelay; - params->iewToFetchDelay = iewToFetchDelay; - params->commitToFetchDelay = commitToFetchDelay; - params->fetchWidth = fetchWidth; - - params->renameToDecodeDelay = renameToDecodeDelay; - params->iewToDecodeDelay = iewToDecodeDelay; - params->commitToDecodeDelay = commitToDecodeDelay; - params->fetchToDecodeDelay = fetchToDecodeDelay; - params->decodeWidth = decodeWidth; - - params->iewToRenameDelay = iewToRenameDelay; - params->commitToRenameDelay = commitToRenameDelay; - params->decodeToRenameDelay = decodeToRenameDelay; - params->renameWidth = renameWidth; - - params->commitToIEWDelay = commitToIEWDelay; - params->renameToIEWDelay = renameToIEWDelay; - params->issueToExecuteDelay = issueToExecuteDelay; - params->dispatchWidth = dispatchWidth; - params->issueWidth = issueWidth; - params->wbWidth = wbWidth; - params->wbDepth = wbDepth; - params->fuPool = fuPool; - - params->iewToCommitDelay = iewToCommitDelay; - params->renameToROBDelay = renameToROBDelay; - params->commitWidth = commitWidth; - params->squashWidth = squashWidth; - params->trapLatency = trapLatency; - - params->backComSize = backComSize; - params->forwardComSize = forwardComSize; - - params->predType = predType; - params->localPredictorSize = localPredictorSize; - params->localCtrBits = localCtrBits; - params->localHistoryTableSize = localHistoryTableSize; - params->localHistoryBits = localHistoryBits; - params->globalPredictorSize = globalPredictorSize; - params->globalCtrBits = globalCtrBits; - params->globalHistoryBits = globalHistoryBits; - params->choicePredictorSize = choicePredictorSize; - params->choiceCtrBits = choiceCtrBits; - - params->BTBEntries = BTBEntries; - params->BTBTagSize = BTBTagSize; - - params->RASSize = RASSize; - - params->LQEntries = LQEntries; - params->SQEntries = SQEntries; - - params->SSITSize = SSITSize; - params->LFSTSize = LFSTSize; - - params->numPhysIntRegs = numPhysIntRegs; - params->numPhysFloatRegs = numPhysFloatRegs; - params->numIQEntries = numIQEntries; - params->numROBEntries = numROBEntries; - - params->smtNumFetchingThreads = smtNumFetchingThreads; - - // Default smtFetchPolicy to "RoundRobin", if necessary. - std::string round_robin_policy = "RoundRobin"; - std::string single_thread = "SingleThread"; - - if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0) - params->smtFetchPolicy = round_robin_policy; - else - params->smtFetchPolicy = smtFetchPolicy; - - params->smtIQPolicy = smtIQPolicy; - params->smtLSQPolicy = smtLSQPolicy; - params->smtLSQThreshold = smtLSQThreshold; - params->smtROBPolicy = smtROBPolicy; - params->smtROBThreshold = smtROBThreshold; - params->smtCommitPolicy = smtCommitPolicy; - - params->instShiftAmt = 2; - - params->deferRegistration = defer_registration; - - params->functionTrace = function_trace; - params->functionTraceStart = function_trace_start; - - cpu = new DerivO3CPU(params); - - return cpu; -} diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh deleted file mode 100644 index 09d73b4a2..000000000 --- a/src/cpu/o3/mips/cpu_impl.hh +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include "config/use_checker.hh" - -#include "arch/mips/faults.hh" -#include "base/cprintf.hh" -#include "base/statistics.hh" -#include "base/timebuf.hh" -#include "cpu/checker/thread_context.hh" -#include "sim/sim_events.hh" -#include "sim/stats.hh" - -#include "cpu/o3/mips/cpu.hh" -#include "cpu/o3/mips/params.hh" -#include "cpu/o3/mips/thread_context.hh" -#include "cpu/o3/comm.hh" -#include "cpu/o3/thread_state.hh" - -template <class Impl> -MipsO3CPU<Impl>::MipsO3CPU(Params *params) - : FullO3CPU<Impl>(this, params) -{ - DPRINTF(O3CPU, "Creating MipsO3CPU object.\n"); - - // Setup any thread state. - this->thread.resize(this->numThreads); - - for (int i = 0; i < this->numThreads; ++i) { - if (i < params->workload.size()) { - DPRINTF(O3CPU, "Workload[%i] process is %#x", - i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], i); - - this->thread[i]->setStatus(ThreadContext::Suspended); - - //usedTids[i] = true; - //threadMap[i] = i; - } else { - //Allocate Empty thread so M5 can use later - //when scheduling threads to CPU - Process* dummy_proc = NULL; - - this->thread[i] = new Thread(this, i, dummy_proc, i); - //usedTids[i] = false; - } - - ThreadContext *tc; - - // Setup the TC that will serve as the interface to the threads/CPU. - MipsTC<Impl> *mips_tc = - new MipsTC<Impl>; - - tc = mips_tc; - - // If we're using a checker, then the TC should be the - // CheckerThreadContext. -#if USE_CHECKER - if (params->checker) { - tc = new CheckerThreadContext<MipsTC<Impl> >( - mips_tc, this->checker); - } -#endif - - mips_tc->cpu = this; - mips_tc->thread = this->thread[i]; - - // Give the thread the TC. - this->thread[i]->tc = tc; - this->thread[i]->setCpuId(params->cpu_id); - - // Add the TC to the CPU's list of TC's. - this->threadContexts.push_back(tc); - } - - for (int i=0; i < this->numThreads; i++) { - this->thread[i]->setFuncExeInst(0); - } - - lockAddr = 0; - lockFlag = false; -} - -template <class Impl> -void -MipsO3CPU<Impl>::regStats() -{ - // Register stats for everything that has stats. - this->fullCPURegStats(); - this->fetch.regStats(); - this->decode.regStats(); - this->rename.regStats(); - this->iew.regStats(); - this->commit.regStats(); -} - - -template <class Impl> -MiscReg -MipsO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscRegNoEffect(misc_reg, tid); -} - -template <class Impl> -MiscReg -MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscReg(misc_reg, tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) -{ - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, - unsigned tid) -{ - this->regFile.setMiscReg(misc_reg, val, tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::squashFromTC(unsigned tid) -{ - this->thread[tid]->inSyscall = true; - this->commit.generateTCEvent(tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::trap(Fault fault, unsigned tid) -{ - // Pass the thread's TC into the invoke method. - fault->invoke(this->threadContexts[tid]); -} - -#if !FULL_SYSTEM - -template <class Impl> -void -MipsO3CPU<Impl>::syscall(int64_t callnum, int tid) -{ - DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); - - DPRINTF(Activity,"Activity: syscall() called.\n"); - - // Temporarily increase this by one to account for the syscall - // instruction. - ++(this->thread[tid]->funcExeInst); - - // Execute the actual syscall. - this->thread[tid]->syscall(callnum); - - // Decrease funcExeInst by one as the normal commit will handle - // incrementing it. - --(this->thread[tid]->funcExeInst); - - DPRINTF(O3CPU, "[tid:%i] Register 2 is %i ", tid, this->readIntReg(2)); -} - -template <class Impl> -TheISA::IntReg -MipsO3CPU<Impl>::getSyscallArg(int i, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - return this->readArchIntReg(MipsISA::ArgumentReg[i], tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid); -} - -template <class Impl> -void -MipsO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) -{ - TheISA::setSyscallReturn(return_value, this->tcBase(tid)); -} -#endif diff --git a/src/cpu/o3/mips/dyn_inst.cc b/src/cpu/o3/mips/dyn_inst.cc deleted file mode 100755 index 216aa7d2c..000000000 --- a/src/cpu/o3/mips/dyn_inst.cc +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include "cpu/o3/mips/dyn_inst_impl.hh" -#include "cpu/o3/mips/impl.hh" - -// Force instantiation of MipsDynInst for all the implementations that -// are needed. -template class MipsDynInst<MipsSimpleImpl>; diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh deleted file mode 100755 index b1a29ccf9..000000000 --- a/src/cpu/o3/mips/dyn_inst.hh +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#ifndef __CPU_O3_MIPS_DYN_INST_HH__ -#define __CPU_O3_MIPS_DYN_INST_HH__ - -#include "arch/isa_traits.hh" -#include "cpu/base_dyn_inst.hh" -#include "cpu/inst_seq.hh" -#include "cpu/o3/mips/cpu.hh" -#include "cpu/o3/mips/impl.hh" - -class Packet; - -/** - * Mostly implementation & ISA specific MipsDynInst. As with most - * other classes in the new CPU model, it is templated on the Impl to - * allow for passing in of all types, such as the CPU type and the ISA - * type. The MipsDynInst serves as the primary interface to the CPU - * for instructions that are executing. - */ -template <class Impl> -class MipsDynInst : public BaseDynInst<Impl> -{ - public: - /** Typedef for the CPU. */ - typedef typename Impl::O3CPU O3CPU; - - /** Logical register index type. */ - typedef TheISA::RegIndex RegIndex; - /** Integer register index type. */ - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - /** Misc register index type. */ - typedef TheISA::MiscReg MiscReg; - - enum { - MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs - MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs - }; - - public: - /** BaseDynInst constructor given a binary instruction. */ - MipsDynInst(StaticInstPtr staticInst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a binary instruction. */ - MipsDynInst(ExtMachInst inst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a static inst pointer. */ - MipsDynInst(StaticInstPtr &_staticInst); - - /** Executes the instruction.*/ - Fault execute(); - - /** Initiates the access. Only valid for memory operations. */ - Fault initiateAcc(); - - /** Completes the access. Only valid for memory operations. */ - Fault completeAcc(PacketPtr pkt); - - private: - /** Initializes variables. */ - void initVars(); - - public: - /** Reads a miscellaneous register. */ - /** TODO: Use thread number from argument if given, will probably not work for MIPS MT as is */ - MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) - { - return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - MiscReg readMiscReg(int misc_reg, unsigned tid = 0) - { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) - { - this->instResult.integer = val; - this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) - { - return this->cpu->setMiscReg(misc_reg, val, - this->threadNumber); - } - - - /** Calls a syscall. */ - void syscall(int64_t callnum); - - public: - - // The register accessor methods provide the index of the - // instruction's operand (e.g., 0 or 1), not the architectural - // register index, to simplify the implementation of register - // renaming. We find the architectural register index by indexing - // into the instruction's own operand index table. Note that a - // raw pointer to the StaticInst is provided instead of a - // ref-counted StaticInstPtr to redice overhead. This is fine as - // long as these methods don't copy the pointer into any long-term - // storage (which is pretty hard to imagine they would have reason - // to do). - - uint64_t readIntRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readIntReg(this->_srcRegIdx[idx]); - } - - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - - FloatReg readFloatRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx]); - } - - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); - } - - /** @todo: Make results into arrays so they can handle multiple dest - * registers. - */ - void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) - { - this->cpu->setIntReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntRegOperand(si, idx, val); - } - - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); - } - - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) - { - return this->cpu->readMiscRegNoEffect( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readMiscReg( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) - { - this->instResult.integer = val; - return this->cpu->setMiscRegNoEffect( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscRegOperand(const StaticInst *si, int idx, - const MiscReg &val) - { - return this->cpu->setMiscReg( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - - uint64_t readRegOtherThread(int misc_reg) - { - panic("MIPS MT not defined for O3 CPU.\n"); - return 0; - } - - void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) - { - panic("MIPS MT not defined for O3 CPU.\n"); - } - - public: - /** Calculates EA part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault calcEA() - { - return this->staticInst->eaCompInst()->execute(this, this->traceData); - } - - /** Does the memory access part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault memAccess() - { - return this->staticInst->memAccInst()->execute(this, this->traceData); - } -}; - -#endif // __CPU_O3_MIPS_DYN_INST_HH__ - diff --git a/src/cpu/o3/mips/dyn_inst_impl.hh b/src/cpu/o3/mips/dyn_inst_impl.hh deleted file mode 100755 index 7e8697b32..000000000 --- a/src/cpu/o3/mips/dyn_inst_impl.hh +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include "cpu/o3/mips/dyn_inst.hh" - -template <class Impl> -MipsDynInst<Impl>::MipsDynInst(StaticInstPtr staticInst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) -{ - initVars(); -} - -template <class Impl> -MipsDynInst<Impl>::MipsDynInst(ExtMachInst inst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(inst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) -{ - initVars(); -} - -template <class Impl> -MipsDynInst<Impl>::MipsDynInst(StaticInstPtr &_staticInst) - : BaseDynInst<Impl>(_staticInst) -{ - initVars(); -} - -template <class Impl> -void -MipsDynInst<Impl>::initVars() -{ - // Make sure to have the renamed register entries set to the same - // as the normal register entries. It will allow the IQ to work - // without any modifications. - for (int i = 0; i < this->staticInst->numDestRegs(); i++) { - this->_destRegIdx[i] = this->staticInst->destRegIdx(i); - } - - for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { - this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); - this->_readySrcRegIdx[i] = 0; - } -} - -template <class Impl> -Fault -MipsDynInst<Impl>::execute() -{ - // @todo: Pretty convoluted way to avoid squashing from happening - // when using the TC during an instruction's execution - // (specifically for instructions that have side-effects that use - // the TC). Fix this. - bool in_syscall = this->thread->inSyscall; - this->thread->inSyscall = true; - - this->fault = this->staticInst->execute(this, this->traceData); - - this->thread->inSyscall = in_syscall; - - return this->fault; -} - -template <class Impl> -Fault -MipsDynInst<Impl>::initiateAcc() -{ - // @todo: Pretty convoluted way to avoid squashing from happening - // when using the TC during an instruction's execution - // (specifically for instructions that have side-effects that use - // the TC). Fix this. - bool in_syscall = this->thread->inSyscall; - this->thread->inSyscall = true; - - this->fault = this->staticInst->initiateAcc(this, this->traceData); - - this->thread->inSyscall = in_syscall; - - return this->fault; -} - -template <class Impl> -Fault -MipsDynInst<Impl>::completeAcc(PacketPtr pkt) -{ - this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); - - return this->fault; -} - -template <class Impl> -void -MipsDynInst<Impl>::syscall(int64_t callnum) -{ - this->cpu->syscall(callnum, this->threadNumber); -} - diff --git a/src/cpu/o3/mips/impl.hh b/src/cpu/o3/mips/impl.hh deleted file mode 100644 index ac7181a19..000000000 --- a/src/cpu/o3/mips/impl.hh +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#ifndef __CPU_O3_MIPS_IMPL_HH__ -#define __CPU_O3_MIPS_IMPL_HH__ - -#include "arch/mips/isa_traits.hh" - -#include "cpu/o3/mips/params.hh" -#include "cpu/o3/cpu_policy.hh" - - -// Forward declarations. -template <class Impl> -class MipsDynInst; - -template <class Impl> -class MipsO3CPU; - -/** Implementation specific struct that defines several key types to the - * CPU, the stages within the CPU, the time buffers, and the DynInst. - * The struct defines the ISA, the CPU policy, the specific DynInst, the - * specific O3CPU, and all of the structs from the time buffers to do - * communication. - * This is one of the key things that must be defined for each hardware - * specific CPU implementation. - */ -struct MipsSimpleImpl -{ - /** The type of MachInst. */ - typedef TheISA::MachInst MachInst; - - /** The CPU policy to be used, which defines all of the CPU stages. */ - typedef SimpleCPUPolicy<MipsSimpleImpl> CPUPol; - - /** The DynInst type to be used. */ - typedef MipsDynInst<MipsSimpleImpl> DynInst; - - /** The refcounted DynInst pointer to be used. In most cases this is - * what should be used, and not DynInst *. - */ - typedef RefCountingPtr<DynInst> DynInstPtr; - - /** The O3CPU type to be used. */ - typedef MipsO3CPU<MipsSimpleImpl> O3CPU; - - /** Same typedef, but for CPUType. BaseDynInst may not always use - * an O3 CPU, so it's clearer to call it CPUType instead in that - * case. - */ - typedef O3CPU CPUType; - - /** The Params to be passed to each stage. */ - typedef MipsSimpleParams Params; - - enum { - MaxWidth = 8, - MaxThreads = 4 - }; -}; - -/** The O3Impl to be used. */ -typedef MipsSimpleImpl O3CPUImpl; - -#endif // __CPU_O3_MIPS_IMPL_HH__ diff --git a/src/cpu/o3/mips/params.hh b/src/cpu/o3/mips/params.hh deleted file mode 100644 index 2688d3fb3..000000000 --- a/src/cpu/o3/mips/params.hh +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#ifndef __CPU_O3_MIPS_PARAMS_HH__ -#define __CPU_O3_MIPS_PARAMS_HH__ - -#include "cpu/o3/cpu.hh" -#include "cpu/o3/params.hh" - -//Forward declarations -namespace MipsISA -{ - class MipsDTB; - class MipsITB; -} -class MemObject; -class Process; -class System; - -/** - * This file defines the parameters that will be used for the MipsO3CPU. - * This must be defined externally so that the Impl can have a params class - * defined that it can pass to all of the individual stages. - */ - -class MipsSimpleParams : public O3Params -{ - public: - MipsSimpleParams() {} - - //Full System Paramater Objects place here - MipsISA::ITB *itb; - MipsISA::DTB *dtb; -}; - -#endif // __CPU_O3_MIPS_PARAMS_HH__ diff --git a/src/cpu/o3/mips/thread_context.cc b/src/cpu/o3/mips/thread_context.cc deleted file mode 100755 index 0061a2a63..000000000 --- a/src/cpu/o3/mips/thread_context.cc +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include "cpu/o3/thread_context.hh" -#include "cpu/o3/thread_context_impl.hh" - -template class O3ThreadContext<MipsSimpleImpl>; - diff --git a/src/cpu/o3/mips/thread_context.hh b/src/cpu/o3/mips/thread_context.hh deleted file mode 100644 index 26b1e2e7f..000000000 --- a/src/cpu/o3/mips/thread_context.hh +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - * Korey Sewell - */ - -#include "arch/mips/types.hh" -#include "cpu/o3/thread_context.hh" - -template <class Impl> -class MipsTC : public O3ThreadContext<Impl> -{ - public: - virtual uint64_t readNextNPC() - { - return this->cpu->readNextNPC(this->thread->readTid()); - } - - virtual void setNextNPC(uint64_t val) - { - this->cpu->setNextNPC(val, this->thread->readTid()); - } - - virtual void changeRegFileContext(TheISA::RegContextParam param, - TheISA::RegContextVal val) - { panic("Not supported on Mips!"); } - - /** This function exits the thread context in the CPU and returns - * 1 if the CPU has no more active threads (meaning it's OK to exit); - * Used in syscall-emulation mode when a thread executes the 'exit' - * syscall. - */ - virtual int exit() - { - this->deallocate(); - - // If there are still threads executing in the system - if (this->cpu->numActiveThreads()) - return 0; // don't exit simulation - else - return 1; // exit simulation - } -}; diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh deleted file mode 100755 index b487778c6..000000000 --- a/src/cpu/o3/params.hh +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_PARAMS_HH__ -#define __CPU_O3_PARAMS_HH__ - -#include "cpu/o3/cpu.hh" - -//Forward declarations -class FUPool; - -/** - * This file defines the parameters that will be used for the O3CPU. - * This must be defined externally so that the Impl can have a params class - * defined that it can pass to all of the individual stages. - */ -class O3Params : public BaseO3CPU::Params -{ - public: - unsigned activity; - - // - // Pointers to key objects - // -#if !FULL_SYSTEM - std::vector<Process *> workload; - Process *process; -#endif // FULL_SYSTEM - - BaseCPU *checker; - - // - // Caches - // - // MemInterface *icacheInterface; - // MemInterface *dcacheInterface; - - unsigned cachePorts; - - // - // Fetch - // - unsigned decodeToFetchDelay; - unsigned renameToFetchDelay; - unsigned iewToFetchDelay; - unsigned commitToFetchDelay; - unsigned fetchWidth; - - // - // Decode - // - unsigned renameToDecodeDelay; - unsigned iewToDecodeDelay; - unsigned commitToDecodeDelay; - unsigned fetchToDecodeDelay; - unsigned decodeWidth; - - // - // Rename - // - unsigned iewToRenameDelay; - unsigned commitToRenameDelay; - unsigned decodeToRenameDelay; - unsigned renameWidth; - - // - // IEW - // - unsigned commitToIEWDelay; - unsigned renameToIEWDelay; - unsigned issueToExecuteDelay; - unsigned dispatchWidth; - unsigned issueWidth; - unsigned wbWidth; - unsigned wbDepth; - FUPool *fuPool; - - // - // Commit - // - unsigned iewToCommitDelay; - unsigned renameToROBDelay; - unsigned commitWidth; - unsigned squashWidth; - Tick trapLatency; - Tick fetchTrapLatency; - - // - // Timebuffer sizes - // - unsigned backComSize; - unsigned forwardComSize; - - // - // Branch predictor (BP, BTB, RAS) - // - std::string predType; - unsigned localPredictorSize; - unsigned localCtrBits; - unsigned localHistoryTableSize; - unsigned localHistoryBits; - unsigned globalPredictorSize; - unsigned globalCtrBits; - unsigned globalHistoryBits; - unsigned choicePredictorSize; - unsigned choiceCtrBits; - - unsigned BTBEntries; - unsigned BTBTagSize; - - unsigned RASSize; - - // - // Load store queue - // - unsigned LQEntries; - unsigned SQEntries; - - // - // Memory dependence - // - unsigned SSITSize; - unsigned LFSTSize; - - // - // Miscellaneous - // - unsigned numPhysIntRegs; - unsigned numPhysFloatRegs; - unsigned numIQEntries; - unsigned numROBEntries; - - //SMT Parameters - unsigned smtNumFetchingThreads; - - std::string smtFetchPolicy; - - std::string smtIQPolicy; - unsigned smtIQThreshold; - - std::string smtLSQPolicy; - unsigned smtLSQThreshold; - - std::string smtCommitPolicy; - - std::string smtROBPolicy; - unsigned smtROBThreshold; - - // Probably can get this from somewhere. - unsigned instShiftAmt; -}; - -#endif // __CPU_O3_ALPHA_PARAMS_HH__ diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh index 97846ed16..f0621c5b5 100644 --- a/src/cpu/o3/ras.hh +++ b/src/cpu/o3/ras.hh @@ -71,6 +71,9 @@ class ReturnAddrStack */ void restore(unsigned top_entry_idx, const Addr &restored_target); + bool empty() { return usedEntries == 0; } + + bool full() { return usedEntries == numEntries; } private: /** Increments the top of stack index. */ inline void incrTos() diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 75d3fa6eb..53ac2d683 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -33,6 +33,7 @@ #define __CPU_O3_REGFILE_HH__ #include "arch/isa_traits.hh" +#include "arch/regfile.hh" #include "arch/types.hh" #include "base/trace.hh" #include "config/full_system.hh" @@ -264,7 +265,7 @@ class PhysRegFile #if FULL_SYSTEM private: - int intrflag; // interrupt flag + int intrflag; // interrupt flag #endif private: diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index b2faffe43..0fdf28b19 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -36,6 +36,8 @@ #include "base/statistics.hh" #include "base/timebuf.hh" +class DerivO3CPUParams; + /** * DefaultRename handles both single threaded and SMT rename. Its * width is specified by the parameters; each cycle it tries to rename @@ -56,7 +58,6 @@ class DefaultRename typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; - typedef typename Impl::Params Params; // Typedefs from the CPUPol typedef typename CPUPol::DecodeStruct DecodeStruct; @@ -107,7 +108,7 @@ class DefaultRename public: /** DefaultRename constructor. */ - DefaultRename(O3CPU *_cpu, Params *params); + DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); /** Returns the name of rename. */ std::string name() const; @@ -440,44 +441,44 @@ class DefaultRename inline void incrFullStat(const FullSource &source); /** Stat for total number of cycles spent squashing. */ - Stats::Scalar<> renameSquashCycles; + Stats::Scalar renameSquashCycles; /** Stat for total number of cycles spent idle. */ - Stats::Scalar<> renameIdleCycles; + Stats::Scalar renameIdleCycles; /** Stat for total number of cycles spent blocking. */ - Stats::Scalar<> renameBlockCycles; + Stats::Scalar renameBlockCycles; /** Stat for total number of cycles spent stalling for a serializing inst. */ - Stats::Scalar<> renameSerializeStallCycles; + Stats::Scalar renameSerializeStallCycles; /** Stat for total number of cycles spent running normally. */ - Stats::Scalar<> renameRunCycles; + Stats::Scalar renameRunCycles; /** Stat for total number of cycles spent unblocking. */ - Stats::Scalar<> renameUnblockCycles; + Stats::Scalar renameUnblockCycles; /** Stat for total number of renamed instructions. */ - Stats::Scalar<> renameRenamedInsts; + Stats::Scalar renameRenamedInsts; /** Stat for total number of squashed instructions that rename discards. */ - Stats::Scalar<> renameSquashedInsts; + Stats::Scalar renameSquashedInsts; /** Stat for total number of times that the ROB starts a stall in rename. */ - Stats::Scalar<> renameROBFullEvents; + Stats::Scalar renameROBFullEvents; /** Stat for total number of times that the IQ starts a stall in rename. */ - Stats::Scalar<> renameIQFullEvents; + Stats::Scalar renameIQFullEvents; /** Stat for total number of times that the LSQ starts a stall in rename. */ - Stats::Scalar<> renameLSQFullEvents; + Stats::Scalar renameLSQFullEvents; /** Stat for total number of times that rename runs out of free registers * to use to rename. */ - Stats::Scalar<> renameFullRegistersEvents; + Stats::Scalar renameFullRegistersEvents; /** Stat for total number of renamed destination registers. */ - Stats::Scalar<> renameRenamedOperands; + Stats::Scalar renameRenamedOperands; /** Stat for total number of source register rename lookups. */ - Stats::Scalar<> renameRenameLookups; + Stats::Scalar renameRenameLookups; /** Stat for total number of committed renaming mappings. */ - Stats::Scalar<> renameCommittedMaps; + Stats::Scalar renameCommittedMaps; /** Stat for total number of mappings that were undone due to a squash. */ - Stats::Scalar<> renameUndoneMaps; + Stats::Scalar renameUndoneMaps; /** Number of serialize instructions handled. */ - Stats::Scalar<> renamedSerializing; + Stats::Scalar renamedSerializing; /** Number of instructions marked as temporarily serializing. */ - Stats::Scalar<> renamedTempSerializing; + Stats::Scalar renamedTempSerializing; /** Number of instructions inserted into skid buffers. */ - Stats::Scalar<> renameSkidInsts; + Stats::Scalar renameSkidInsts; }; #endif // __CPU_O3_RENAME_HH__ diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 49c885753..81647b133 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -35,9 +35,10 @@ #include "arch/regfile.hh" #include "config/full_system.hh" #include "cpu/o3/rename.hh" +#include "params/DerivO3CPU.hh" template <class Impl> -DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params) +DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) : cpu(_cpu), iewToRenameDelay(params->iewToRenameDelay), decodeToRenameDelay(params->decodeToRenameDelay), @@ -46,7 +47,7 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params) commitWidth(params->commitWidth), resumeSerialize(false), resumeUnblocking(false), - numThreads(params->numberOfThreads), + numThreads(params->numThreads), maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) { _status = Inactive; diff --git a/src/cpu/o3/sparc/cpu.cc b/src/cpu/o3/sparc/cpu.cc deleted file mode 100644 index 1546a2b88..000000000 --- a/src/cpu/o3/sparc/cpu.cc +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "cpu/o3/sparc/impl.hh" -#include "cpu/o3/sparc/cpu_impl.hh" -#include "cpu/o3/sparc/dyn_inst.hh" - -// Force instantiation of SparcO3CPU for all the implementations that are -// needed. Consider merging this and sparc_dyn_inst.cc, and maybe all -// classes that depend on a certain impl, into one file (sparc_impl.cc?). -template class SparcO3CPU<SparcSimpleImpl>; diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh deleted file mode 100644 index 3fd193e0f..000000000 --- a/src/cpu/o3/sparc/cpu.hh +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#ifndef __CPU_O3_SPARC_CPU_HH__ -#define __CPU_O3_SPARC_CPU_HH__ - -#include "arch/sparc/regfile.hh" -#include "arch/sparc/types.hh" -#include "cpu/thread_context.hh" -#include "cpu/o3/cpu.hh" -#include "sim/byteswap.hh" - -class EndQuiesceEvent; -namespace Kernel { - class Statistics; -}; - -class TranslatingPort; - -/** - * SparcO3CPU class. Derives from the FullO3CPU class, and - * implements all ISA and implementation specific functions of the - * CPU. This is the CPU class that is used for the SimObjects, and is - * what is given to the DynInsts. Most of its state exists in the - * FullO3CPU; the state is has is mainly for ISA specific - * functionality. - */ -template <class Impl> -class SparcO3CPU : public FullO3CPU<Impl> -{ - public: - typedef O3ThreadState<Impl> ImplState; - typedef O3ThreadState<Impl> Thread; - typedef typename Impl::Params Params; - - /** Constructs an AlphaO3CPU with the given parameters. */ - SparcO3CPU(Params *params); - - /** Registers statistics. */ - void regStats(); - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); - - /** Reads a misc. register, including any side effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); - - /** Sets a miscellaneous register. */ - void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); - - /** Sets a misc. register, including any side effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, - unsigned tid); - - /** Initiates a squash of all in-flight instructions for a given - * thread. The source of the squash is an external update of - * state through the TC. - */ - void squashFromTC(unsigned tid); - -#if FULL_SYSTEM - /** Posts an interrupt. */ - void post_interrupt(int int_num, int index); - /** HW return from error interrupt. */ - Fault hwrei(unsigned tid); - - bool simPalCheck(int palFunc, unsigned tid); - - /** Returns the Fault for any valid interrupt. */ - Fault getInterrupts(); - - /** Processes any an interrupt fault. */ - void processInterrupts(Fault interrupt); - - /** Halts the CPU. */ - void halt() { panic("Halt not implemented!\n"); } -#endif - - /** Traps to handle given fault. */ - void trap(Fault fault, unsigned tid); - -#if !FULL_SYSTEM - /** Executes a syscall. - * @todo: Determine if this needs to be virtual. - */ - void syscall(int64_t callnum, int tid); - /** Gets a syscall argument. */ - TheISA::IntReg getSyscallArg(int i, int tid); - - /** Used to shift args for indirect syscall. */ - void setSyscallArg(int i, TheISA::IntReg val, int tid); - - /** Sets the return value of a syscall. */ - void setSyscallReturn(SyscallReturn return_value, int tid); -#endif - - /** CPU read function, forwards read to LSQ. */ - template <class T> - Fault read(RequestPtr &req, T &data, int load_idx) - { - return this->iew.ldstQueue.read(req, data, load_idx); - } - - /** CPU write function, forwards write to LSQ. */ - template <class T> - Fault write(RequestPtr &req, T &data, int store_idx) - { - return this->iew.ldstQueue.write(req, data, store_idx); - } - - Addr lockAddr; - - /** Temporary fix for the lock flag, works in the UP case. */ - bool lockFlag; -}; - -#endif // __CPU_O3_SPARC_CPU_HH__ diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc deleted file mode 100644 index b08845b4e..000000000 --- a/src/cpu/o3/sparc/cpu_builder.cc +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include <string> - -#include "config/full_system.hh" -#include "config/use_checker.hh" -#include "cpu/base.hh" -#include "cpu/o3/sparc/cpu.hh" -#include "cpu/o3/sparc/impl.hh" -#include "cpu/o3/sparc/params.hh" -#include "cpu/o3/fu_pool.hh" -#include "params/DerivO3CPU.hh" - -class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl> -{ - public: - DerivO3CPU(SparcSimpleParams *p) - : SparcO3CPU<SparcSimpleImpl>(p) - { } -}; - -DerivO3CPU * -DerivO3CPUParams::create() -{ - DerivO3CPU *cpu; - -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - int actual_num_threads = 1; -#else - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - int actual_num_threads = - (numThreads >= workload.size()) ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); - } -#endif - - SparcSimpleParams *params = new SparcSimpleParams; - - params->clock = clock; - params->phase = phase; - - params->tracer = tracer; - - params->name = name; - params->numberOfThreads = actual_num_threads; - params->cpu_id = cpu_id; - params->activity = activity; - - params->itb = itb; - params->dtb = dtb; - - params->system = system; -#if FULL_SYSTEM - params->profile = profile; - - params->do_quiesce = do_quiesce; - params->do_checkpoint_insts = do_checkpoint_insts; - params->do_statistics_insts = do_statistics_insts; -#else - params->workload = workload; -#endif // FULL_SYSTEM - -#if USE_CHECKER - params->checker = checker; -#endif - - params->max_insts_any_thread = max_insts_any_thread; - params->max_insts_all_threads = max_insts_all_threads; - params->max_loads_any_thread = max_loads_any_thread; - params->max_loads_all_threads = max_loads_all_threads; - params->progress_interval = progress_interval; - - // - // Caches - // - params->cachePorts = cachePorts; - - params->decodeToFetchDelay = decodeToFetchDelay; - params->renameToFetchDelay = renameToFetchDelay; - params->iewToFetchDelay = iewToFetchDelay; - params->commitToFetchDelay = commitToFetchDelay; - params->fetchWidth = fetchWidth; - - params->renameToDecodeDelay = renameToDecodeDelay; - params->iewToDecodeDelay = iewToDecodeDelay; - params->commitToDecodeDelay = commitToDecodeDelay; - params->fetchToDecodeDelay = fetchToDecodeDelay; - params->decodeWidth = decodeWidth; - - params->iewToRenameDelay = iewToRenameDelay; - params->commitToRenameDelay = commitToRenameDelay; - params->decodeToRenameDelay = decodeToRenameDelay; - params->renameWidth = renameWidth; - - params->commitToIEWDelay = commitToIEWDelay; - params->renameToIEWDelay = renameToIEWDelay; - params->issueToExecuteDelay = issueToExecuteDelay; - params->dispatchWidth = dispatchWidth; - params->issueWidth = issueWidth; - params->wbWidth = wbWidth; - params->wbDepth = wbDepth; - params->fuPool = fuPool; - - params->iewToCommitDelay = iewToCommitDelay; - params->renameToROBDelay = renameToROBDelay; - params->commitWidth = commitWidth; - params->squashWidth = squashWidth; - params->trapLatency = trapLatency; - - params->backComSize = backComSize; - params->forwardComSize = forwardComSize; - - params->predType = predType; - params->localPredictorSize = localPredictorSize; - params->localCtrBits = localCtrBits; - params->localHistoryTableSize = localHistoryTableSize; - params->localHistoryBits = localHistoryBits; - params->globalPredictorSize = globalPredictorSize; - params->globalCtrBits = globalCtrBits; - params->globalHistoryBits = globalHistoryBits; - params->choicePredictorSize = choicePredictorSize; - params->choiceCtrBits = choiceCtrBits; - - params->BTBEntries = BTBEntries; - params->BTBTagSize = BTBTagSize; - - params->RASSize = RASSize; - - params->LQEntries = LQEntries; - params->SQEntries = SQEntries; - - params->SSITSize = SSITSize; - params->LFSTSize = LFSTSize; - - params->numPhysIntRegs = numPhysIntRegs; - params->numPhysFloatRegs = numPhysFloatRegs; - params->numIQEntries = numIQEntries; - params->numROBEntries = numROBEntries; - - params->smtNumFetchingThreads = smtNumFetchingThreads; - - // Default smtFetchPolicy to "RoundRobin", if necessary. - std::string round_robin_policy = "RoundRobin"; - std::string single_thread = "SingleThread"; - - if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0) - params->smtFetchPolicy = round_robin_policy; - else - params->smtFetchPolicy = smtFetchPolicy; - - params->smtIQPolicy = smtIQPolicy; - params->smtLSQPolicy = smtLSQPolicy; - params->smtLSQThreshold = smtLSQThreshold; - params->smtROBPolicy = smtROBPolicy; - params->smtROBThreshold = smtROBThreshold; - params->smtCommitPolicy = smtCommitPolicy; - - params->instShiftAmt = 2; - - params->deferRegistration = defer_registration; - - params->functionTrace = function_trace; - params->functionTraceStart = function_trace_start; - - cpu = new DerivO3CPU(params); - - return cpu; -} diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh deleted file mode 100644 index 068057fc0..000000000 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "config/use_checker.hh" - -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" -#include "base/cprintf.hh" -#include "base/statistics.hh" -#include "base/timebuf.hh" -#include "cpu/checker/thread_context.hh" -#include "sim/sim_events.hh" -#include "sim/stats.hh" - -#include "cpu/o3/sparc/cpu.hh" -#include "cpu/o3/sparc/params.hh" -#include "cpu/o3/sparc/thread_context.hh" -#include "cpu/o3/comm.hh" -#include "cpu/o3/thread_state.hh" - -#if FULL_SYSTEM -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/kernel_stats.hh" -#include "cpu/quiesce_event.hh" -#include "sim/sim_exit.hh" -#include "sim/system.hh" -#endif - -template <class Impl> -SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(this, params) -{ - DPRINTF(O3CPU, "Creating SparcO3CPU object.\n"); - - // Setup any thread state. - this->thread.resize(this->numThreads); - - for (int i = 0; i < this->numThreads; ++i) { -#if FULL_SYSTEM - // SMT is not supported in FS mode yet. - assert(this->numThreads == 1); - this->thread[i] = new Thread(this, 0); - this->thread[i]->setStatus(ThreadContext::Suspended); -#else - if (i < params->workload.size()) { - DPRINTF(O3CPU, "Workload[%i] process is %#x", - i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], i); - - this->thread[i]->setStatus(ThreadContext::Suspended); - - //usedTids[i] = true; - //threadMap[i] = i; - } else { - //Allocate Empty thread so M5 can use later - //when scheduling threads to CPU - Process* dummy_proc = NULL; - - this->thread[i] = new Thread(this, i, dummy_proc, i); - //usedTids[i] = false; - } -#endif // !FULL_SYSTEM - - ThreadContext *tc; - - // Setup the TC that will serve as the interface to the threads/CPU. - SparcTC<Impl> *sparc_tc = new SparcTC<Impl>; - - tc = sparc_tc; - - // If we're using a checker, then the TC should be the - // CheckerThreadContext. -#if USE_CHECKER - if (params->checker) { - tc = new CheckerThreadContext<SparcTC<Impl> >( - sparc_tc, this->checker); - } -#endif - - sparc_tc->cpu = this; - sparc_tc->thread = this->thread[i]; - -#if FULL_SYSTEM - // Setup quiesce event. - this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); -#endif - // Give the thread the TC. - this->thread[i]->tc = tc; - this->thread[i]->setCpuId(params->cpu_id); - - // Add the TC to the CPU's list of TC's. - this->threadContexts.push_back(tc); - } - - for (int i=0; i < this->numThreads; i++) { - this->thread[i]->setFuncExeInst(0); - } - - lockAddr = 0; - lockFlag = false; -} - -template <class Impl> -void -SparcO3CPU<Impl>::regStats() -{ - // Register stats for everything that has stats. - this->fullCPURegStats(); - this->fetch.regStats(); - this->decode.regStats(); - this->rename.regStats(); - this->iew.regStats(); - this->commit.regStats(); -} - - -template <class Impl> -TheISA::MiscReg -SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscRegNoEffect(misc_reg, tid); -} - -template <class Impl> -TheISA::MiscReg -SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) -{ - return this->regFile.readMiscReg(misc_reg, tid); -} - -template <class Impl> -void -SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, - const SparcISA::MiscReg &val, unsigned tid) -{ - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); -} - -template <class Impl> -void -SparcO3CPU<Impl>::setMiscReg(int misc_reg, - const SparcISA::MiscReg &val, unsigned tid) -{ - this->regFile.setMiscReg(misc_reg, val, tid); -} - -template <class Impl> -void -SparcO3CPU<Impl>::squashFromTC(unsigned tid) -{ - this->thread[tid]->inSyscall = true; - this->commit.generateTCEvent(tid); -} - -#if FULL_SYSTEM - -template <class Impl> -void -SparcO3CPU<Impl>::post_interrupt(int int_num, int index) -{ - BaseCPU::post_interrupt(int_num, index); - - if (this->thread[0]->status() == ThreadContext::Suspended) { - DPRINTF(IPI,"Suspended Processor awoke\n"); - this->threadContexts[0]->activate(); - } -} - -template <class Impl> -Fault -SparcO3CPU<Impl>::hwrei(unsigned tid) -{ - panic("This doesn't make sense for SPARC\n"); - return NoFault; -} - -template <class Impl> -bool -SparcO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) -{ - panic("This doesn't make sense for SPARC\n"); - return true; -} - -template <class Impl> -Fault -SparcO3CPU<Impl>::getInterrupts() -{ - // Check if there are any outstanding interrupts - return this->interrupts.getInterrupt(this->threadContexts[0]); -} - -template <class Impl> -void -SparcO3CPU<Impl>::processInterrupts(Fault interrupt) -{ - // Check for interrupts here. For now can copy the code that - // exists within isa_fullsys_traits.hh. Also assume that thread 0 - // is the one that handles the interrupts. - // @todo: Possibly consolidate the interrupt checking code. - // @todo: Allow other threads to handle interrupts. - - assert(interrupt != NoFault); - this->interrupts.updateIntrInfo(this->threadContexts[0]); - - DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->trap(interrupt, 0); -} - -#endif // FULL_SYSTEM - -template <class Impl> -void -SparcO3CPU<Impl>::trap(Fault fault, unsigned tid) -{ - // Pass the thread's TC into the invoke method. - fault->invoke(this->threadContexts[tid]); -} - -#if !FULL_SYSTEM - -template <class Impl> -void -SparcO3CPU<Impl>::syscall(int64_t callnum, int tid) -{ - DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); - - DPRINTF(Activity,"Activity: syscall() called.\n"); - - // Temporarily increase this by one to account for the syscall - // instruction. - ++(this->thread[tid]->funcExeInst); - - // Execute the actual syscall. - this->thread[tid]->syscall(callnum); - - // Decrease funcExeInst by one as the normal commit will handle - // incrementing it. - --(this->thread[tid]->funcExeInst); -} - -template <class Impl> -TheISA::IntReg -SparcO3CPU<Impl>::getSyscallArg(int i, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg[i]); - TheISA::IntReg val = this->readArchIntReg(idx, tid); - if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) - val = bits(val, 31, 0); - return val; -} - -template <class Impl> -void -SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) -{ - assert(i < TheISA::NumArgumentRegs); - TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg[i]); - this->setArchIntReg(idx, val, tid); -} - -template <class Impl> -void -SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) -{ - TheISA::setSyscallReturn(return_value, this->tcBase(tid)); -} -#endif diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh deleted file mode 100644 index a7ab6cd79..000000000 --- a/src/cpu/o3/sparc/dyn_inst.hh +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __CPU_O3_SPARC_DYN_INST_HH__ -#define __CPU_O3_SPARC_DYN_INST_HH__ - -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" -#include "cpu/base_dyn_inst.hh" -#include "cpu/inst_seq.hh" -#include "cpu/o3/sparc/cpu.hh" -#include "cpu/o3/sparc/impl.hh" - -class Packet; - -/** - * Mostly implementation & ISA specific SparcDynInst. As with most - * other classes in the new CPU model, it is templated on the Impl to - * allow for passing in of all types, such as the CPU type and the ISA - * type. The SparcDynInst serves as the primary interface to the CPU - * for instructions that are executing. - */ -template <class Impl> -class SparcDynInst : public BaseDynInst<Impl> -{ - public: - /** Typedef for the CPU. */ - typedef typename Impl::O3CPU O3CPU; - - public: - /** BaseDynInst constructor given a binary instruction. */ - SparcDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a binary instruction. */ - SparcDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu); - - /** BaseDynInst constructor given a static inst pointer. */ - SparcDynInst(StaticInstPtr &_staticInst); - - /** Executes the instruction.*/ - Fault execute(); - - /** Initiates the access. Only valid for memory operations. */ - Fault initiateAcc(); - - /** Completes the access. Only valid for memory operations. */ - Fault completeAcc(PacketPtr pkt); - - private: - /** Initializes variables. */ - void initVars(); - - public: - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg) - { - return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscReg(int misc_reg) - { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val) - { - this->instResult.integer = val; - return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val) - { - return this->cpu->setMiscReg(misc_reg, val, - this->threadNumber); - } - - /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) - { - return this->cpu->readMiscRegNoEffect( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Reads a misc. register, including any side-effects the read - * might have as defined by the architecture. - */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readMiscReg( - si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - this->threadNumber); - } - - /** Sets a misc. register. */ - void setMiscRegOperandNoEffect(const StaticInst * si, - int idx, const TheISA::MiscReg &val) - { - this->instResult.integer = val; - return this->cpu->setMiscRegNoEffect( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - - /** Sets a misc. register, including any side-effects the write - * might have as defined by the architecture. - */ - void setMiscRegOperand( - const StaticInst *si, int idx, const TheISA::MiscReg &val) - { - return this->cpu->setMiscReg( - si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, - val, this->threadNumber); - } - -#if FULL_SYSTEM - /** Calls hardware return from error interrupt. */ - Fault hwrei(); - /** Traps to handle specified fault. */ - void trap(Fault fault); - bool simPalCheck(int palFunc); -#else - /** Calls a syscall. */ - void syscall(int64_t callnum); -#endif - - public: - - // The register accessor methods provide the index of the - // instruction's operand (e.g., 0 or 1), not the architectural - // register index, to simplify the implementation of register - // renaming. We find the architectural register index by indexing - // into the instruction's own operand index table. Note that a - // raw pointer to the StaticInst is provided instead of a - // ref-counted StaticInstPtr to redice overhead. This is fine as - // long as these methods don't copy the pointer into any long-term - // storage (which is pretty hard to imagine they would have reason - // to do). - - uint64_t readIntRegOperand(const StaticInst *si, int idx) - { - uint64_t val = this->cpu->readIntReg(this->_srcRegIdx[idx]); - DPRINTF(Sparc, "Reading int reg %d (%d, %d) as %x\n", (int)this->_flatSrcRegIdx[idx], (int)this->_srcRegIdx[idx], idx, val); - return val; - } - - TheISA::FloatReg readFloatRegOperand(const StaticInst *si, - int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - - TheISA::FloatReg readFloatRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx]); - } - - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, - int idx, int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); - } - - /** @todo: Make results into arrays so they can handle multiple dest - * registers. - */ - void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) - { - DPRINTF(Sparc, "Setting int reg %d (%d, %d) to %x\n", (int)this->_flatDestRegIdx[idx], (int)this->_destRegIdx[idx], idx, val); - this->cpu->setIntReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntRegOperand(si, idx, val); - } - - void setFloatRegOperand(const StaticInst *si, int idx, - TheISA::FloatReg val, int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); - } - - void setFloatRegOperand(const StaticInst *si, int idx, TheISA::FloatReg val) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, - TheISA::FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, - int idx, TheISA::FloatRegBits val) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - public: - /** Calculates EA part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault calcEA() - { - return this->staticInst->eaCompInst()->execute(this, this->traceData); - } - - /** Does the memory access part of a memory instruction. Currently unused, - * though it may be useful in the future if we want to split - * memory operations into EA calculation and memory access parts. - */ - Fault memAccess() - { - return this->staticInst->memAccInst()->execute(this, this->traceData); - } -}; - -#endif // __CPU_O3_SPARC_DYN_INST_HH__ - diff --git a/src/cpu/o3/sparc/dyn_inst_impl.hh b/src/cpu/o3/sparc/dyn_inst_impl.hh deleted file mode 100644 index 6bfe97717..000000000 --- a/src/cpu/o3/sparc/dyn_inst_impl.hh +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "cpu/o3/sparc/dyn_inst.hh" - -template <class Impl> -SparcDynInst<Impl>::SparcDynInst(StaticInstPtr staticInst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) -{ - initVars(); -} - -template <class Impl> -SparcDynInst<Impl>::SparcDynInst(TheISA::ExtMachInst inst, - Addr PC, Addr NPC, Addr microPC, - Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, - InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(inst, PC, NPC, microPC, - Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) -{ - initVars(); -} - -template <class Impl> -SparcDynInst<Impl>::SparcDynInst(StaticInstPtr &_staticInst) - : BaseDynInst<Impl>(_staticInst) -{ - initVars(); -} - -template <class Impl> -void -SparcDynInst<Impl>::initVars() -{ - // Make sure to have the renamed register entries set to the same - // as the normal register entries. It will allow the IQ to work - // without any modifications. - for (int i = 0; i < this->staticInst->numDestRegs(); i++) { - this->_destRegIdx[i] = this->staticInst->destRegIdx(i); - } - - for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { - this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); - this->_readySrcRegIdx[i] = 0; - } -} - -template <class Impl> -Fault -SparcDynInst<Impl>::execute() -{ - // @todo: Pretty convoluted way to avoid squashing from happening - // when using the TC during an instruction's execution - // (specifically for instructions that have side-effects that use - // the TC). Fix this. - bool in_syscall = this->thread->inSyscall; - this->thread->inSyscall = true; - - this->fault = this->staticInst->execute(this, this->traceData); - - this->thread->inSyscall = in_syscall; - - return this->fault; -} - -template <class Impl> -Fault -SparcDynInst<Impl>::initiateAcc() -{ - // @todo: Pretty convoluted way to avoid squashing from happening - // when using the TC during an instruction's execution - // (specifically for instructions that have side-effects that use - // the TC). Fix this. - bool in_syscall = this->thread->inSyscall; - this->thread->inSyscall = true; - - this->fault = this->staticInst->initiateAcc(this, this->traceData); - - this->thread->inSyscall = in_syscall; - - return this->fault; -} - -template <class Impl> -Fault -SparcDynInst<Impl>::completeAcc(PacketPtr pkt) -{ - this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); - - return this->fault; -} - -#if FULL_SYSTEM -template <class Impl> -Fault -SparcDynInst<Impl>::hwrei() -{ - return NoFault; -} - -template <class Impl> -void -SparcDynInst<Impl>::trap(Fault fault) -{ - this->cpu->trap(fault, this->threadNumber); -} - -template <class Impl> -bool -SparcDynInst<Impl>::simPalCheck(int palFunc) -{ - panic("simPalCheck called, but there's no PAL in SPARC!\n"); - return false; -} -#else -template <class Impl> -void -SparcDynInst<Impl>::syscall(int64_t callnum) -{ - this->cpu->syscall(callnum, this->threadNumber); -} -#endif - diff --git a/src/cpu/o3/sparc/params.hh b/src/cpu/o3/sparc/params.hh deleted file mode 100644 index 09f523818..000000000 --- a/src/cpu/o3/sparc/params.hh +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __CPU_O3_SPARC_PARAMS_HH__ -#define __CPU_O3_SPARC_PARAMS_HH__ - -#include "cpu/o3/cpu.hh" -#include "cpu/o3/params.hh" - -//Forward declarations -namespace SparcISA -{ - class DTB; - class ITB; -} -class MemObject; -class Process; -class System; - -/** - * This file defines the parameters that will be used for the AlphaO3CPU. - * This must be defined externally so that the Impl can have a params class - * defined that it can pass to all of the individual stages. - */ - -class SparcSimpleParams : public O3Params -{ - public: - - SparcISA::ITB *itb; - SparcISA::DTB *dtb; -}; - -#endif // __CPU_O3_SPARC_PARAMS_HH__ diff --git a/src/cpu/o3/sparc/thread_context.cc b/src/cpu/o3/sparc/thread_context.cc deleted file mode 100755 index d85aff502..000000000 --- a/src/cpu/o3/sparc/thread_context.cc +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "cpu/o3/thread_context.hh" -#include "cpu/o3/thread_context_impl.hh" - -template class O3ThreadContext<SparcSimpleImpl>; - diff --git a/src/cpu/o3/sparc/thread_context.hh b/src/cpu/o3/sparc/thread_context.hh deleted file mode 100644 index 7497959e4..000000000 --- a/src/cpu/o3/sparc/thread_context.hh +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/sparc/types.hh" -#include "cpu/o3/thread_context.hh" - -template <class Impl> -class SparcTC : public O3ThreadContext<Impl> -{ - public: -#if FULL_SYSTEM - /** Returns pointer to the quiesce event. */ - virtual EndQuiesceEvent *getQuiesceEvent() - { - return this->thread->quiesceEvent; - } -#endif - - virtual uint64_t readNextNPC() - { - return this->cpu->readNextNPC(this->thread->readTid()); - } - - virtual void setNextNPC(uint64_t val) - { - this->cpu->setNextNPC(val, this->thread->readTid()); - } - - virtual void changeRegFileContext(TheISA::RegContextParam param, - TheISA::RegContextVal val) - { - //XXX Ignore this for now. This -really- needs to get fixed. - } - - - /** This function exits the thread context in the CPU and returns - * 1 if the CPU has no more active threads (meaning it's OK to exit); - * Used in syscall-emulation mode when a thread executes the 'exit' - * syscall. - */ - virtual int exit() - { - this->deallocate(); - - // If there are still threads executing in the system - if (this->cpu->numActiveThreads()) - return 0; // don't exit simulation - else - return 1; // exit simulation - } -}; diff --git a/src/cpu/o3/alpha/thread_context.cc b/src/cpu/o3/thread_context.cc index 4a02715bc..0d8c67643 100755 --- a/src/cpu/o3/alpha/thread_context.cc +++ b/src/cpu/o3/thread_context.cc @@ -26,11 +26,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Kevin Lim - * Korey Sewell */ #include "cpu/o3/thread_context.hh" #include "cpu/o3/thread_context_impl.hh" +#include "cpu/o3/impl.hh" -template class O3ThreadContext<AlphaSimpleImpl>; +template class O3ThreadContext<O3CPUImpl>; diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index e7bdc6de5..f3058925d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -75,16 +75,21 @@ class O3ThreadContext : public ThreadContext /** Returns a pointer to this CPU. */ virtual BaseCPU *getCpuPtr() { return cpu; } - /** Sets this CPU's ID. */ - virtual void setCpuId(int id) { cpu->setCpuId(id); } - /** Reads this CPU's ID. */ - virtual int readCpuId() { return cpu->readCpuId(); } + virtual int cpuId() { return cpu->cpuId(); } + + virtual int contextId() { return thread->contextId(); } + + virtual void setContextId(int id) { thread->setContextId(id); } + + /** Returns this thread's ID number. */ + virtual int threadId() { return thread->threadId(); } + virtual void setThreadId(int id) { return thread->setThreadId(id); } -#if FULL_SYSTEM /** Returns a pointer to the system. */ virtual System *getSystemPtr() { return cpu->system; } +#if FULL_SYSTEM /** Returns a pointer to physical memory. */ virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } @@ -94,11 +99,9 @@ class O3ThreadContext : public ThreadContext virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } - virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL); - - void delVirtPort(VirtualPort *vp); + virtual VirtualPort *getVirtPort(); - virtual void connectMemPorts() { thread->connectMemPorts(); } + virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } #else virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } @@ -153,9 +156,6 @@ class O3ThreadContext : public ThreadContext /** Samples the function profiling information. */ virtual void profileSample(); #endif - /** Returns this thread's ID number. */ - virtual int getThreadNum() { return thread->readTid(); } - /** Returns the instruction this thread is currently committing. * Only used when an instruction faults. */ @@ -191,36 +191,36 @@ class O3ThreadContext : public ThreadContext /** Reads this thread's PC. */ virtual uint64_t readPC() - { return cpu->readPC(thread->readTid()); } + { return cpu->readPC(thread->threadId()); } /** Sets this thread's PC. */ virtual void setPC(uint64_t val); /** Reads this thread's next PC. */ virtual uint64_t readNextPC() - { return cpu->readNextPC(thread->readTid()); } + { return cpu->readNextPC(thread->threadId()); } /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); virtual uint64_t readMicroPC() - { return cpu->readMicroPC(thread->readTid()); } + { return cpu->readMicroPC(thread->threadId()); } virtual void setMicroPC(uint64_t val); virtual uint64_t readNextMicroPC() - { return cpu->readNextMicroPC(thread->readTid()); } + { return cpu->readNextMicroPC(thread->threadId()); } virtual void setNextMicroPC(uint64_t val); /** Reads a miscellaneous register. */ virtual MiscReg readMiscRegNoEffect(int misc_reg) - { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } + { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ virtual MiscReg readMiscReg(int misc_reg) - { return cpu->readMiscReg(misc_reg, thread->readTid()); } + { return cpu->readMiscReg(misc_reg, thread->threadId()); } /** Sets a misc. register. */ virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); @@ -247,22 +247,48 @@ class O3ThreadContext : public ThreadContext virtual bool misspeculating() { return false; } #if !FULL_SYSTEM - /** Gets a syscall argument by index. */ - virtual IntReg getSyscallArg(int i); - - /** Sets a syscall argument. */ - virtual void setSyscallArg(int i, IntReg val); - - /** Sets the syscall return value. */ - virtual void setSyscallReturn(SyscallReturn return_value); - /** Executes a syscall in SE mode. */ virtual void syscall(int64_t callnum) - { return cpu->syscall(callnum, thread->readTid()); } + { return cpu->syscall(callnum, thread->threadId()); } /** Reads the funcExeInst counter. */ virtual Counter readFuncExeInst() { return thread->funcExeInst; } +#else + /** Returns pointer to the quiesce event. */ + virtual EndQuiesceEvent *getQuiesceEvent() + { + return this->thread->quiesceEvent; + } #endif + + virtual uint64_t readNextNPC() + { + return this->cpu->readNextNPC(this->thread->threadId()); + } + + virtual void setNextNPC(uint64_t val) + { +#if THE_ISA == ALPHA_ISA + panic("Not supported on Alpha!"); +#endif + this->cpu->setNextNPC(val, this->thread->threadId()); + } + + /** This function exits the thread context in the CPU and returns + * 1 if the CPU has no more active threads (meaning it's OK to exit); + * Used in syscall-emulation mode when a thread executes the 'exit' + * syscall. + */ + virtual int exit() + { + this->deallocate(); + + // If there are still threads executing in the system + if (this->cpu->numActiveThreads()) + return 0; // don't exit simulation + else + return 1; // exit simulation + } }; #endif diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 865d58635..fc8b66b83 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -36,16 +36,9 @@ #if FULL_SYSTEM template <class Impl> VirtualPort * -O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc) +O3ThreadContext<Impl>::getVirtPort() { - if (!src_tc) - return thread->getVirtPort(); - - VirtualPort *vp; - - vp = new VirtualPort("tc-vport", src_tc); - thread->connectToMemFunc(vp); - return vp; + return thread->getVirtPort(); } template <class Impl> @@ -61,16 +54,16 @@ void O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) { // some things should already be set up -#if FULL_SYSTEM assert(getSystemPtr() == old_context->getSystemPtr()); -#else +#if !FULL_SYSTEM assert(getProcessPtr() == old_context->getProcessPtr()); #endif // copy over functional state setStatus(old_context->status()); copyArchRegs(old_context); - setCpuId(old_context->readCpuId()); + setContextId(old_context->contextId()); + setThreadId(old_context->threadId()); #if !FULL_SYSTEM thread->funcExeInst = old_context->readFuncExeInst(); @@ -97,24 +90,12 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) thread->trapPending = false; } -#if FULL_SYSTEM -template <class Impl> -void -O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) -{ - if (vp != thread->getVirtPort()) { - vp->removeConn(); - delete vp; - } -} -#endif - template <class Impl> void O3ThreadContext<Impl>::activate(int delay) { DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", - getThreadNum()); + threadId()); if (thread->status() == ThreadContext::Active) return; @@ -124,14 +105,14 @@ O3ThreadContext<Impl>::activate(int delay) #endif if (thread->status() == ThreadContext::Unallocated) { - cpu->activateWhenReady(thread->readTid()); + cpu->activateWhenReady(thread->threadId()); return; } thread->setStatus(ThreadContext::Active); // status() == Suspended - cpu->activateContext(thread->readTid(), delay); + cpu->activateContext(thread->threadId(), delay); } template <class Impl> @@ -139,7 +120,7 @@ void O3ThreadContext<Impl>::suspend(int delay) { DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", - getThreadNum()); + threadId()); if (thread->status() == ThreadContext::Suspended) return; @@ -151,14 +132,14 @@ O3ThreadContext<Impl>::suspend(int delay) /* #if FULL_SYSTEM // Don't change the status from active if there are pending interrupts - if (cpu->check_interrupts()) { + if (cpu->checkInterrupts()) { assert(status() == ThreadContext::Active); return; } #endif */ thread->setStatus(ThreadContext::Suspended); - cpu->suspendContext(thread->readTid()); + cpu->suspendContext(thread->threadId()); } template <class Impl> @@ -166,13 +147,13 @@ void O3ThreadContext<Impl>::deallocate(int delay) { DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", - getThreadNum(), delay); + threadId(), delay); if (thread->status() == ThreadContext::Unallocated) return; thread->setStatus(ThreadContext::Unallocated); - cpu->deallocateContext(thread->readTid(), true, delay); + cpu->deallocateContext(thread->threadId(), true, delay); } template <class Impl> @@ -180,13 +161,13 @@ void O3ThreadContext<Impl>::halt(int delay) { DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", - getThreadNum()); + threadId()); if (thread->status() == ThreadContext::Halted) return; thread->setStatus(ThreadContext::Halted); - cpu->haltContext(thread->readTid()); + cpu->haltContext(thread->threadId()); } template <class Impl> @@ -264,7 +245,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) { // This function will mess things up unless the ROB is empty and // there are no instructions in the pipeline. - unsigned tid = thread->readTid(); + unsigned tid = thread->threadId(); PhysRegIndex renamed_reg; // First loop through the integer registers. @@ -311,7 +292,7 @@ uint64_t O3ThreadContext<Impl>::readIntReg(int reg_idx) { reg_idx = TheISA::flattenIntIndex(this, reg_idx); - return cpu->readArchIntReg(reg_idx, thread->readTid()); + return cpu->readArchIntReg(reg_idx, thread->threadId()); } template <class Impl> @@ -321,9 +302,9 @@ O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: - return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); + return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); case 64: - return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); + return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); default: panic("Unsupported width!"); return 0; @@ -335,7 +316,7 @@ TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); + return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); } template <class Impl> @@ -344,7 +325,7 @@ O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); + return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } template <class Impl> @@ -352,7 +333,7 @@ TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); + return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } template <class Impl> @@ -360,11 +341,11 @@ void O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) { reg_idx = TheISA::flattenIntIndex(this, reg_idx); - cpu->setArchIntReg(reg_idx, val, thread->readTid()); + cpu->setArchIntReg(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -375,16 +356,16 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: - cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); + cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); break; case 64: - cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); + cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); break; } // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -393,10 +374,10 @@ void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); + cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -407,11 +388,11 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, { DPRINTF(Fault, "Setting floatint register through the TC!\n"); reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); + cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -420,11 +401,11 @@ void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); + cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -432,11 +413,11 @@ template <class Impl> void O3ThreadContext<Impl>::setPC(uint64_t val) { - cpu->setPC(val, thread->readTid()); + cpu->setPC(val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -444,11 +425,11 @@ template <class Impl> void O3ThreadContext<Impl>::setNextPC(uint64_t val) { - cpu->setNextPC(val, thread->readTid()); + cpu->setNextPC(val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -456,11 +437,11 @@ template <class Impl> void O3ThreadContext<Impl>::setMicroPC(uint64_t val) { - cpu->setMicroPC(val, thread->readTid()); + cpu->setMicroPC(val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -468,11 +449,11 @@ template <class Impl> void O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) { - cpu->setNextMicroPC(val, thread->readTid()); + cpu->setNextMicroPC(val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -480,11 +461,11 @@ template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); + cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } @@ -493,36 +474,11 @@ void O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) { - cpu->setMiscReg(misc_reg, val, thread->readTid()); + cpu->setMiscReg(misc_reg, val, thread->threadId()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); + cpu->squashFromTC(thread->threadId()); } } -#if !FULL_SYSTEM - -template <class Impl> -TheISA::IntReg -O3ThreadContext<Impl>::getSyscallArg(int i) -{ - return cpu->getSyscallArg(i, thread->readTid()); -} - -template <class Impl> -void -O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) -{ - cpu->setSyscallArg(i, val, thread->readTid()); -} - -template <class Impl> -void -O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) -{ - cpu->setSyscallReturn(return_value, thread->readTid()); -} - -#endif // FULL_SYSTEM - diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index d8720b3ab..1f0e7a3bb 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -77,11 +77,11 @@ struct O3ThreadState : public ThreadState { #if FULL_SYSTEM O3ThreadState(O3CPU *_cpu, int _thread_num) - : ThreadState(_cpu, -1, _thread_num), + : ThreadState(_cpu, _thread_num), cpu(_cpu), inSyscall(0), trapPending(0) { - if (cpu->params->profile) { - profile = new FunctionProfile(cpu->params->system->kernelSymtab); + if (cpu->params()->profile) { + profile = new FunctionProfile(cpu->params()->system->kernelSymtab); Callback *cb = new MakeCallback<O3ThreadState, &O3ThreadState::dumpFuncProfile>(this); @@ -96,7 +96,7 @@ struct O3ThreadState : public ThreadState { } #else O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid) - : ThreadState(_cpu, -1, _thread_num, _process, _asid), + : ThreadState(_cpu, _thread_num, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) { } #endif |