diff options
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/mips/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 6 |
3 files changed, 12 insertions, 6 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 1754300d2..7f8f0547b 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -293,14 +293,16 @@ template <class Impl> TheISA::IntReg AlphaO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); } template <class Impl> void AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { - this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index d1135f048..09d73b4a2 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -196,14 +196,16 @@ template <class Impl> TheISA::IntReg MipsO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(MipsISA::ArgumentReg[i], tid); } template <class Impl> void MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) { - this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 2e398577e..068057fc0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -270,8 +270,9 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); TheISA::IntReg val = this->readArchIntReg(idx, tid); if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) val = bits(val, 31, 0); @@ -282,8 +283,9 @@ template <class Impl> void SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); this->setArchIntReg(idx, val, tid); } |