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-rw-r--r--src/cpu/o3/fetch_impl.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f9cc78c18..fcee2daa6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Translate the instruction request.
fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
- false, true);
+ BaseTLB::Execute);
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.