diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 15 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 7 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 5 |
4 files changed, 23 insertions, 7 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 45f5bc02b..31398c3d9 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -631,7 +631,8 @@ DefaultCommit<Impl>::tick() wroteToTimeBuffer = false; _nextStatus = Inactive; - if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { + if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() && + interrupt == NoFault) { cpu->signalDrained(); drainPending = false; return; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index e8fc968b7..64c54e26a 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -55,6 +55,7 @@ #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "debug/Activity.hh" +#include "debug/Drain.hh" #include "debug/O3CPU.hh" #include "debug/Quiesce.hh" #include "enums/MemoryMode.hh" @@ -260,7 +261,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) if (!deferRegistration) { _status = Running; } else { - _status = Idle; + _status = SwitchedOut; } if (params->checker) { @@ -1119,9 +1120,8 @@ FullO3CPU<Impl>::drain(Event *drain_event) DPRINTF(O3CPU, "Switching out\n"); // If the CPU isn't doing anything, then return immediately. - if (_status == Idle || _status == SwitchedOut) { + if (_status == SwitchedOut) return 0; - } drainCount = 0; fetch.drain(); @@ -1142,6 +1142,8 @@ FullO3CPU<Impl>::drain(Event *drain_event) wakeCPU(); activityRec.activity(); + DPRINTF(Drain, "CPU not drained\n"); + return 1; } else { return 0; @@ -1160,7 +1162,7 @@ FullO3CPU<Impl>::resume() changeState(SimObject::Running); - if (_status == SwitchedOut || _status == Idle) + if (_status == SwitchedOut) return; assert(system->getMemoryMode() == Enums::timing); @@ -1183,6 +1185,7 @@ FullO3CPU<Impl>::signalDrained() BaseCPU::switchOut(); if (drainEvent) { + DPRINTF(Drain, "CPU done draining, processing drain event\n"); drainEvent->process(); drainEvent = NULL; } @@ -1237,6 +1240,10 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) assert(!tickEvent.scheduled() || tickEvent.squashed()); + FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); + if (oldO3CPU) + globalSeqNum = oldO3CPU->globalSeqNum; + // @todo: Figure out how to properly select the tid to put onto // the active threads list. ThreadID tid = 0; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index b6eb25c08..81d70bd61 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -132,8 +132,10 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) // Get the size of an instruction. instSize = sizeof(TheISA::MachInst); - for (int i = 0; i < Impl::MaxThreads; i++) + for (int i = 0; i < Impl::MaxThreads; i++) { + cacheData[i] = NULL; decoder[i] = new TheISA::Decoder(NULL); + } } template <class Impl> @@ -346,7 +348,8 @@ DefaultFetch<Impl>::setIcache() for (ThreadID tid = 0; tid < numThreads; tid++) { // Create space to store a cache line. - cacheData[tid] = new uint8_t[cacheBlkSize]; + if (!cacheData[tid]) + cacheData[tid] = new uint8_t[cacheBlkSize]; cacheDataPC[tid] = 0; cacheDataValid[tid] = false; } diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 7093b5fee..b886a2259 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -335,6 +335,11 @@ class LSQUnit { std::memset(data, 0, sizeof(data)); } + ~SQEntry() + { + inst = NULL; + } + /** Constructs a store queue entry for a given instruction. */ SQEntry(DynInstPtr &_inst) : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), |