4 files changed, 19 insertions, 14 deletions

diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc
index c99428617..3ff3d86bc 100644
--- a/src/cpu/o3/checker.cc
+++ b/src/cpu/o3/checker.cc
@@ -82,6 +82,7 @@ O3CheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c5421302d..9de1bf6b4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -241,6 +241,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
                  TheISA::NumMiscRegs * numThreads,
                  TheISA::ZeroReg),
 
+      isa(numThreads, NULL),
+
       icachePort(&fetch, this),
       dcachePort(&iew.ldstQueue, this),
 
@@ -340,6 +342,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         bool bindRegs = (tid <= active_threads - 1);
 
+        isa[tid] = params->isa[tid];
+
         commitRenameMap[tid].init(TheISA::NumIntRegs,
                                   params->numPhysIntRegs,
                                   lreg_idx,            //Index for Logical. Regs
@@ -1285,7 +1289,7 @@ template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return this->isa[tid].readMiscRegNoEffect(misc_reg);
+    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
@@ -1293,7 +1297,7 @@ TheISA::MiscReg
 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 {
     miscRegfileReads++;
-    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
+    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
 }
 
 template <class Impl>
@@ -1301,7 +1305,7 @@ void
 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
+    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
@@ -1310,7 +1314,7 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
     miscRegfileWrites++;
-    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
+    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1f9a8da6c..06e1ea336 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -634,7 +634,7 @@ class FullO3CPU : public BaseO3CPU
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;
 
-    TheISA::ISA isa[Impl::MaxThreads];
+    std::vector<TheISA::ISA *> isa;
 
     /** Instruction port. Note that it has to appear after the fetch stage. */
     IcachePort icachePort;
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 38e7c5dec..9d60a9700 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -219,14 +219,14 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::clearArchRegs()
 {
-    cpu->isa[thread->threadId()].clear();
+    cpu->isa[thread->threadId()]->clear();
 }
 
 template <class Impl>
 uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
@@ -234,7 +234,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     return cpu->readArchFloatReg(reg_idx, thread->threadId());
 }
 
@@ -242,7 +242,7 @@ template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -250,7 +250,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -260,7 +260,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -270,7 +270,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -298,14 +298,14 @@ template <class Impl>
 int
 O3ThreadContext<Impl>::flattenIntIndex(int reg)
 {
-    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+    return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
 }
 
 template <class Impl>
 int
 O3ThreadContext<Impl>::flattenFloatIndex(int reg)
 {
-    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+    return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
 }
 
 template <class Impl>