diff options
Diffstat (limited to 'src/cpu/o3')
| -rwxr-xr-x | src/cpu/o3/SConscript | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index ad61ad228..2de106d8b 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -32,6 +32,16 @@ import sys Import('*') +if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: + Source('2bit_local_pred.cc') + Source('btb.cc') + Source('ras.cc') + Source('tournament_pred.cc') + + TraceFlag('CommitRate') + TraceFlag('IEW') + TraceFlag('IQ') + if 'O3CPU' in env['CPU_MODELS']: SimObject('FUPool.py') SimObject('FuncUnitConfig.py') @@ -56,6 +66,21 @@ if 'O3CPU' in env['CPU_MODELS']: Source('scoreboard.cc') Source('store_set.cc') + TraceFlag('FreeList') + TraceFlag('LSQ') + TraceFlag('LSQUnit') + TraceFlag('MemDepUnit') + TraceFlag('O3CPU') + TraceFlag('ROB') + TraceFlag('Rename') + TraceFlag('Scoreboard') + TraceFlag('StoreSet') + TraceFlag('Writeback') + + CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', + 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', + 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) + if env['TARGET_ISA'] == 'alpha': Source('alpha/cpu.cc') Source('alpha/cpu_builder.cc') @@ -77,10 +102,3 @@ if 'O3CPU' in env['CPU_MODELS']: if env['USE_CHECKER']: SimObject('O3Checker.py') Source('checker_builder.cc') - -if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: - Source('2bit_local_pred.cc') - Source('btb.cc') - Source('ras.cc') - Source('tournament_pred.cc') - |