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-rw-r--r--src/cpu/o3/commit.hh2
-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc6
-rw-r--r--src/cpu/o3/cpu.hh6
-rw-r--r--src/cpu/o3/dyn_inst.hh4
-rw-r--r--src/cpu/o3/inst_queue.hh2
-rw-r--r--src/cpu/o3/inst_queue_impl.hh2
-rw-r--r--src/cpu/o3/lsq_unit.hh2
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh2
9 files changed, 16 insertions, 12 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 27bdd20c5..80e42fa8b 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -97,7 +97,7 @@ class DefaultCommit
TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
void process();
- const char *description();
+ const char *description() const;
};
/** Overall commit status. Used to determine if the CPU can deschedule
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 89df257e9..ee0f2bb59 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -65,7 +65,7 @@ DefaultCommit<Impl>::TrapEvent::process()
template <class Impl>
const char *
-DefaultCommit<Impl>::TrapEvent::description()
+DefaultCommit<Impl>::TrapEvent::description() const
{
return "Trap";
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 5908062aa..8eb17d23b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -80,7 +80,7 @@ FullO3CPU<Impl>::TickEvent::process()
template <class Impl>
const char *
-FullO3CPU<Impl>::TickEvent::description()
+FullO3CPU<Impl>::TickEvent::description() const
{
return "FullO3CPU tick";
}
@@ -109,7 +109,7 @@ FullO3CPU<Impl>::ActivateThreadEvent::process()
template <class Impl>
const char *
-FullO3CPU<Impl>::ActivateThreadEvent::description()
+FullO3CPU<Impl>::ActivateThreadEvent::description() const
{
return "FullO3CPU \"Activate Thread\"";
}
@@ -141,7 +141,7 @@ FullO3CPU<Impl>::DeallocateContextEvent::process()
template <class Impl>
const char *
-FullO3CPU<Impl>::DeallocateContextEvent::description()
+FullO3CPU<Impl>::DeallocateContextEvent::description() const
{
return "FullO3CPU \"Deallocate Context\"";
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 162e377e1..e902968c1 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -136,7 +136,7 @@ class FullO3CPU : public BaseO3CPU
/** Processes a tick event, calling tick() on the CPU. */
void process();
/** Returns the description of the tick event. */
- const char *description();
+ const char *description() const;
};
/** The tick event used for scheduling CPU ticks. */
@@ -178,7 +178,7 @@ class FullO3CPU : public BaseO3CPU
void process();
/** Returns the description of the event. */
- const char *description();
+ const char *description() const;
};
/** Schedule thread to activate , regardless of its current state. */
@@ -229,7 +229,7 @@ class FullO3CPU : public BaseO3CPU
void setRemove(bool _remove) { remove = _remove; }
/** Returns the description of the event. */
- const char *description();
+ const char *description() const;
};
/** Schedule cpu to deallocate thread context.*/
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index c37f8007e..a1f9e0591 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -49,6 +49,10 @@
template <class Impl> class X86DynInst;
struct X86SimpleImpl;
typedef X86DynInst<X86SimpleImpl> O3DynInst;
+#elif THE_ISA == ARM_ISA
+ template <class Impl> class ArmDynInst;
+ struct ArmSimpleImpl;
+ typedef ArmDynInst<ArmSimpleImpl> O3DynInst;
#else
#error "O3DynInst not defined for this ISA"
#endif
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 9d7c457ca..d0f503977 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -105,7 +105,7 @@ class InstructionQueue
InstructionQueue<Impl> *iq_ptr);
virtual void process();
- virtual const char *description();
+ virtual const char *description() const;
void setFreeFU() { freeFU = true; }
};
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index b14a63a17..fb06f20df 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -58,7 +58,7 @@ InstructionQueue<Impl>::FUCompletion::process()
template <class Impl>
const char *
-InstructionQueue<Impl>::FUCompletion::description()
+InstructionQueue<Impl>::FUCompletion::description() const
{
return "Functional unit completion";
}
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index be9224099..128a71dbc 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -273,7 +273,7 @@ class LSQUnit {
void process();
/** Returns the description of this event. */
- const char *description();
+ const char *description() const;
private:
/** Instruction whose results are being written back. */
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 71b416c9c..e6ff5e931 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -67,7 +67,7 @@ LSQUnit<Impl>::WritebackEvent::process()
template<class Impl>
const char *
-LSQUnit<Impl>::WritebackEvent::description()
+LSQUnit<Impl>::WritebackEvent::description() const
{
return "Store writeback";
}