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-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc6
-rw-r--r--src/cpu/o3/fetch_impl.hh6
-rw-r--r--src/cpu/o3/inst_queue_impl.hh2
-rw-r--r--src/cpu/o3/lsq_impl.hh7
-rw-r--r--src/cpu/o3/lsq_unit.hh11
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh32
7 files changed, 17 insertions, 49 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 9411c6c62..f263383ae 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -67,7 +67,7 @@ template <class Impl>
const char *
DefaultCommit<Impl>::TrapEvent::description()
{
- return "Trap event";
+ return "Trap";
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 20ed5df63..cae6ae20c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -83,7 +83,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::TickEvent::description()
{
- return "FullO3CPU tick event";
+ return "FullO3CPU tick";
}
template <class Impl>
@@ -112,7 +112,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::ActivateThreadEvent::description()
{
- return "FullO3CPU \"Activate Thread\" event";
+ return "FullO3CPU \"Activate Thread\"";
}
template <class Impl>
@@ -144,7 +144,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::DeallocateContextEvent::description()
{
- return "FullO3CPU \"Deallocate Context\" event";
+ return "FullO3CPU \"Deallocate Context\"";
}
template <class Impl>
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d1c660258..ab411c7fe 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -628,12 +628,6 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Now do the timing access to see whether or not the instruction
// exists within the cache.
if (!icachePort->sendTiming(data_pkt)) {
- if (data_pkt->result == Packet::BadAddress) {
- fault = TheISA::genMachineCheckFault();
- delete mem_req;
- memReq[tid] = NULL;
- warn("Bad address!\n");
- }
assert(retryPkt == NULL);
assert(retryTid == -1);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bbdd4ddd5..47f019ebe 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -60,7 +60,7 @@ template <class Impl>
const char *
InstructionQueue<Impl>::FUCompletion::description()
{
- return "Functional unit completion event";
+ return "Functional unit completion";
}
template <class Impl>
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index b4a6a02da..10c0afd38 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -84,9 +84,10 @@ LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
}
else {
- //else it is a coherence request, maybe you need to do something
- warn("Recieved a coherence request (Invalidate?), 03CPU doesn't"
- "update LSQ for these\n");
+ // must be a snoop
+
+ // @TODO someday may need to process invalidations in LSQ here
+ // to provide stronger consistency model
}
return true;
}
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index cc33e025d..be9224099 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -643,7 +643,10 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
PacketPtr data_pkt =
- new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ new Packet(req,
+ (req->isLocked() ?
+ MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
@@ -653,8 +656,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
data_pkt->senderState = state;
if (!dcachePort->sendTiming(data_pkt)) {
- Packet::Result result = data_pkt->result;
-
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
@@ -663,10 +664,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
req = NULL;
- if (result == Packet::BadAddress) {
- return TheISA::genMachineCheckFault();
- }
-
// If the access didn't succeed, tell the LSQ by setting
// the retry thread id.
lsq->setRetryTid(lsqID);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index bde4f8079..8b2e82d8e 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -69,7 +69,7 @@ template<class Impl>
const char *
LSQUnit<Impl>::WritebackEvent::description()
{
- return "Store writeback event";
+ return "Store writeback";
}
template<class Impl>
@@ -647,7 +647,9 @@ LSQUnit<Impl>::writebackStores()
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
- MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
+ MemCmd command =
+ req->isSwap() ? MemCmd::SwapReq :
+ (req->isLocked() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
PacketPtr data_pkt = new Packet(req, command,
Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
@@ -690,9 +692,6 @@ LSQUnit<Impl>::writebackStores()
}
if (!dcachePort->sendTiming(data_pkt)) {
- if (data_pkt->result == Packet::BadAddress) {
- panic("LSQ sent out a bad address for a completed store!");
- }
// Need to handle becoming blocked on a store.
DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
"retry later\n",
@@ -844,26 +843,6 @@ LSQUnit<Impl>::storePostSend(PacketPtr pkt)
#endif
}
- if (pkt->result != Packet::Success) {
- DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
- storeWBIdx);
-
- DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
- storeQueue[storeWBIdx].inst->seqNum);
-
- //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
-
- //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
-
- // @todo: Increment stat here.
- } else {
- DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
- storeWBIdx);
-
- DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
- storeQueue[storeWBIdx].inst->seqNum);
- }
-
incrStIdx(storeWBIdx);
}
@@ -952,9 +931,6 @@ LSQUnit<Impl>::recvRetry()
assert(retryPkt != NULL);
if (dcachePort->sendTiming(retryPkt)) {
- if (retryPkt->result == Packet::BadAddress) {
- panic("LSQ sent out a bad address for a completed store!");
- }
storePostSend(retryPkt);
retryPkt = NULL;
isStoreBlocked = false;
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 21:20:09 +0000