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-rw-r--r--src/cpu/o3/FUPool.py40
-rw-r--r--src/cpu/o3/FuncUnitConfig.py69
-rw-r--r--src/cpu/o3/O3CPU.py153
-rw-r--r--src/cpu/o3/O3Checker.py43
-rwxr-xr-xsrc/cpu/o3/SConscript5
-rw-r--r--src/cpu/o3/fetch.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh13
-rw-r--r--src/cpu/o3/lsq.hh4
8 files changed, 323 insertions, 8 deletions
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
new file mode 100644
index 000000000..4f07f9867
--- /dev/null
+++ b/src/cpu/o3/FUPool.py
@@ -0,0 +1,40 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+from FuncUnitConfig import *
+
+class FUPool(SimObject):
+ type = 'FUPool'
+ FUList = VectorParam.FUDesc("list of FU's for this pool")
+
+class DefaultFUPool(FUPool):
+ FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+ WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
new file mode 100644
index 000000000..954381f86
--- /dev/null
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -0,0 +1,69 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu') ]
+ count = 6
+
+class IntMultDiv(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3),
+ OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+ count=2
+
+class FP_ALU(FUDesc):
+ opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+ OpDesc(opClass='FloatCmp', opLat=2),
+ OpDesc(opClass='FloatCvt', opLat=2) ]
+ count = 4
+
+class FP_MultDiv(FUDesc):
+ opList = [ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+ OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+ count = 2
+
+class ReadPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead') ]
+ count = 0
+
+class WritePort(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite') ]
+ count = 0
+
+class RdWrPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+ count = 4
+
+class IprPort(FUDesc):
+ opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+ count = 1
+
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
new file mode 100644
index 000000000..e031faefa
--- /dev/null
+++ b/src/cpu/o3/O3CPU.py
@@ -0,0 +1,153 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+from FUPool import *
+
+if build_env['USE_CHECKER']:
+ from O3Checker import O3Checker
+
+class DerivO3CPU(BaseCPU):
+ type = 'DerivO3CPU'
+ activity = Param.Unsigned(0, "Initial count")
+ numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+ if build_env['FULL_SYSTEM']:
+ profile = Param.Latency('0ns', "trace the kernel stack")
+ if build_env['USE_CHECKER']:
+ if not build_env['FULL_SYSTEM']:
+ checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+ exitOnError=False,
+ updateOnError=True,
+ warnOnlyOnLoadError=False),
+ "checker")
+ else:
+ checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
+ warnOnlyOnLoadError=False), "checker")
+ checker.itb = Parent.itb
+ checker.dtb = Parent.dtb
+
+ cachePorts = Param.Unsigned("Cache Ports")
+ icache_port = Port("Instruction Port")
+ dcache_port = Port("Data Port")
+ _mem_ports = ['icache_port', 'dcache_port']
+
+ decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
+ renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
+ iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
+ "delay")
+ commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
+ fetchWidth = Param.Unsigned(8, "Fetch width")
+
+ renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
+ iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
+ "delay")
+ commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
+ fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
+ decodeWidth = Param.Unsigned(8, "Decode width")
+
+ iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
+ "delay")
+ commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
+ decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
+ renameWidth = Param.Unsigned(8, "Rename width")
+
+ commitToIEWDelay = Param.Unsigned(1, "Commit to "
+ "Issue/Execute/Writeback delay")
+ renameToIEWDelay = Param.Unsigned(2, "Rename to "
+ "Issue/Execute/Writeback delay")
+ issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
+ "to the IEW stage)")
+ dispatchWidth = Param.Unsigned(8, "Dispatch width")
+ issueWidth = Param.Unsigned(8, "Issue width")
+ wbWidth = Param.Unsigned(8, "Writeback width")
+ wbDepth = Param.Unsigned(1, "Writeback depth")
+ fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
+
+ iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
+ "delay")
+ renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
+ commitWidth = Param.Unsigned(8, "Commit width")
+ squashWidth = Param.Unsigned(8, "Squash width")
+ trapLatency = Param.Tick(13, "Trap latency")
+ fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
+
+ backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
+ forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
+
+ predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
+ localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
+ localCtrBits = Param.Unsigned(2, "Bits per counter")
+ localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
+ localHistoryBits = Param.Unsigned(11, "Bits for the local history")
+ globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
+ globalCtrBits = Param.Unsigned(2, "Bits per counter")
+ globalHistoryBits = Param.Unsigned(13, "Bits of history")
+ choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
+ choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
+
+ BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
+ BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
+
+ RASSize = Param.Unsigned(16, "RAS size")
+
+ LQEntries = Param.Unsigned(32, "Number of load queue entries")
+ SQEntries = Param.Unsigned(32, "Number of store queue entries")
+ LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
+ SSITSize = Param.Unsigned(1024, "Store set ID table size")
+
+ numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
+
+ numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
+ numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
+ "registers")
+ numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
+ numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
+
+ instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
+
+ function_trace = Param.Bool(False, "Enable function trace")
+ function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+ smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
+ smtFetchPolicy = Param.String("SMT Fetch policy")
+ smtLSQPolicy = Param.String("SMT LSQ Sharing Policy")
+ smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
+ smtIQPolicy = Param.String("SMT IQ Sharing Policy")
+ smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
+ smtROBPolicy = Param.String("SMT ROB Sharing Policy")
+ smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
+ smtCommitPolicy = Param.String("SMT Commit Policy")
+
+ def addPrivateSplitL1Caches(self, ic, dc):
+ BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
+ self.icache.tgts_per_mshr = 20
+ self.dcache.tgts_per_mshr = 20
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
new file mode 100644
index 000000000..43a71d67b
--- /dev/null
+++ b/src/cpu/o3/O3Checker.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.params import *
+from m5 import build_env
+from BaseCPU import BaseCPU
+
+class O3Checker(BaseCPU):
+ type = 'O3Checker'
+ exitOnError = Param.Bool(False, "Exit on an error")
+ updateOnError = Param.Bool(False,
+ "Update the checker with the main CPU's state on an error")
+ warnOnlyOnLoadError = Param.Bool(False,
+ "If a load result is incorrect, only print a warning and do not exit")
+ function_trace = Param.Bool(False, "Enable function trace")
+ function_trace_start = Param.Tick(0, "Cycle to start function trace")
+ if build_env['FULL_SYSTEM']:
+ profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index bb1dfb613..ad61ad228 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -33,6 +33,10 @@ import sys
Import('*')
if 'O3CPU' in env['CPU_MODELS']:
+ SimObject('FUPool.py')
+ SimObject('FuncUnitConfig.py')
+ SimObject('O3CPU.py')
+
Source('base_dyn_inst.cc')
Source('bpred_unit.cc')
Source('commit.cc')
@@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']:
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
if env['USE_CHECKER']:
+ SimObject('O3Checker.py')
Source('checker_builder.cc')
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 7645a226c..d954bd1e7 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -100,8 +100,8 @@ class DefaultFetch
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3ae7bc402..0fd1e7bac 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -29,6 +29,9 @@
* Korey Sewell
*/
+#include <algorithm>
+#include <cstring>
+
#include "config/use_checker.hh"
#include "arch/isa_traits.hh"
@@ -48,8 +51,6 @@
#include "sim/system.hh"
#endif // FULL_SYSTEM
-#include <algorithm>
-
template<class Impl>
void
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
@@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
return;
}
- memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
+ memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
cacheDataValid[tid] = true;
if (!drainPending) {
@@ -1116,7 +1117,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
(&cacheData[tid][offset]));
predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(fetch_PC, 0, inst);
+ predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
ext_inst = predecoder.getExtMachInst();
staticInst = StaticInstPtr(ext_inst);
@@ -1153,10 +1154,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
tid, instruction->staticInst->disassemble(fetch_PC));
+#if TRACING_ON
instruction->traceData =
Trace::getInstRecord(curTick, cpu->tcBase(tid),
instruction->staticInst,
instruction->readPC());
+#else
+ instruction->traceData = NULL;
+#endif
///FIXME This needs to be more robust in dealing with delay slots
predicted_branch |=
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index fd8f878a7..06de608e0 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -316,8 +316,8 @@ class LSQ {
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 18:18:43 +0000