diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 18 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 6 |
3 files changed, 11 insertions, 16 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 0ff515855..2480211e4 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -611,8 +611,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) } // Build packet here. - PacketPtr data_pkt = new Packet(mem_req, - MemCmd::ReadReq, Packet::Broadcast); + PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq); data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); cacheDataPC[tid] = block_PC; diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 44898eb38..44c3df0bf 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -605,18 +605,15 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, ThreadContext *thread = cpu->tcBase(lsqID); Tick delay; - PacketPtr data_pkt = - new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); if (!TheISA::HasUnalignedMemAcc || !sreqLow) { data_pkt->dataStatic(load_inst->memData); delay = TheISA::handleIprRead(thread, data_pkt); } else { assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr()); - PacketPtr fst_data_pkt = - new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast); - PacketPtr snd_data_pkt = - new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast); + PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq); + PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq); fst_data_pkt->dataStatic(load_inst->memData); snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); @@ -689,8 +686,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, "addr %#x, data %#x\n", store_idx, req->getVaddr(), data); - PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq, - Packet::Broadcast); + PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); data_pkt->dataStatic(load_inst->memData); WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); @@ -772,7 +768,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, if (!lsq->cacheBlocked()) { MemCmd command = req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; - PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); + PacketPtr data_pkt = new Packet(req, command); PacketPtr fst_data_pkt = NULL; PacketPtr snd_data_pkt = NULL; @@ -791,8 +787,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, } else { // Create the split packets. - fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast); - snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); + fst_data_pkt = new Packet(sreqLow, command); + snd_data_pkt = new Packet(sreqHigh, command); fst_data_pkt->dataStatic(load_inst->memData); snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 2de349242..f4182e30d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -823,13 +823,13 @@ LSQUnit<Impl>::writebackStores() if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { // Build a single data packet if the store isn't split. - data_pkt = new Packet(req, command, Packet::Broadcast); + data_pkt = new Packet(req, command); data_pkt->dataStatic(inst->memData); data_pkt->senderState = state; } else { // Create two packets if the store is split in two. - data_pkt = new Packet(sreqLow, command, Packet::Broadcast); - snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); + data_pkt = new Packet(sreqLow, command); + snd_data_pkt = new Packet(sreqHigh, command); data_pkt->dataStatic(inst->memData); snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); |