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-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh35
-rw-r--r--src/cpu/o3/commit_impl.hh6
-rw-r--r--src/cpu/o3/fetch_impl.hh60
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh35
5 files changed, 73 insertions, 66 deletions
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 4e2ce63df..c340a806a 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -147,27 +147,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
@@ -175,35 +176,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
public:
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 1527efe1a..3178410a8 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1180,16 +1180,16 @@ DefaultCommit<Impl>::getInsts()
rename_idx < fromRename->size;
rename_idx++) {
DynInstPtr inst = fromRename->insts[rename_idx];
- int tid = inst->threadNumber;
if (!inst->isSquashed()) {
DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
- "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+ "skidBuffer.\n", inst->readPC(), inst->seqNum,
+ inst->threadNumber);
skidBuffer.push(inst);
} else {
DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- inst->readPC(), inst->seqNum, tid);
+ inst->readPC(), inst->seqNum, inst->threadNumber);
}
}
}
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f9e90614a..6cff52429 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
" RoundRobin,LSQcount,IQcount}\n");
}
- // Size of cache block.
- cacheBlkSize = 64;
-
- // Create mask to get rid of offset bits.
- cacheBlkMask = (cacheBlkSize - 1);
-
- for (int tid=0; tid < numThreads; tid++) {
-
- fetchStatus[tid] = Running;
-
- priorityList.push_back(tid);
-
- memReq[tid] = NULL;
-
- // Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
- cacheDataPC[tid] = 0;
- cacheDataValid[tid] = false;
-
- delaySlotInfo[tid].branchSeqNum = -1;
- delaySlotInfo[tid].numInsts = 0;
- delaySlotInfo[tid].targetAddr = 0;
- delaySlotInfo[tid].targetReady = false;
-
- stalls[tid].decode = false;
- stalls[tid].rename = false;
- stalls[tid].iew = false;
- stalls[tid].commit = false;
- }
-
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
}
@@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
+
+ // Size of cache block.
+ cacheBlkSize = icachePort->peerBlockSize();
+
+ // Create mask to get rid of offset bits.
+ cacheBlkMask = (cacheBlkSize - 1);
+
+ for (int tid=0; tid < numThreads; tid++) {
+
+ fetchStatus[tid] = Running;
+
+ priorityList.push_back(tid);
+
+ memReq[tid] = NULL;
+
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+
+ delaySlotInfo[tid].branchSeqNum = -1;
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
+
+ stalls[tid].decode = false;
+ stalls[tid].rename = false;
+ stalls[tid].iew = false;
+ stalls[tid].commit = false;
+ }
}
template<class Impl>
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 379724166..7ce3dc9cb 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
- if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
+ if (!(inst->req && inst->req->isUncacheable()) ||
+ inst->isAtCommit()) {
inst->setExecuted();
}
iewStage->instToCommit(inst);
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index bf82168ce..009a08012 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -136,27 +136,28 @@ class MipsDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
@@ -164,35 +165,37 @@ class MipsDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
public:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 00:34:57 +0000