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-rw-r--r--src/cpu/o3/cpu.cc4
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/o3/dyn_inst.hh2
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh2
-rw-r--r--src/cpu/o3/fetch.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh2
6 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2055d63b6..fdbbd5c14 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1095,7 +1095,7 @@ FullO3CPU<Impl>::getInterrupts()
template <class Impl>
void
-FullO3CPU<Impl>::processInterrupts(Fault interrupt)
+FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
{
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
@@ -1112,7 +1112,7 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
template <class Impl>
void
-FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
+FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst)
{
// Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid], inst);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f5f9897e7..cfed216c3 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -498,7 +498,7 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);
@@ -509,7 +509,7 @@ class FullO3CPU : public BaseO3CPU
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 52ea1101a..ea961092d 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -230,7 +230,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
- void trap(Fault fault);
+ void trap(const Fault &fault);
bool simPalCheck(int palFunc);
/** Emulates a syscall. */
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 4e1492077..e51054f8d 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -225,7 +225,7 @@ BaseO3DynInst<Impl>::hwrei()
template <class Impl>
void
-BaseO3DynInst<Impl>::trap(Fault fault)
+BaseO3DynInst<Impl>::trap(const Fault &fault)
{
this->cpu->trap(fault, this->threadNumber, this->staticInst);
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 4d01610d9..968d94029 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -100,7 +100,7 @@ class DefaultFetch
{}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode)
{
assert(mode == BaseTLB::Execute);
@@ -294,7 +294,7 @@ class DefaultFetch
* @return Any fault that occured.
*/
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
- void finishTranslation(Fault fault, RequestPtr mem_req);
+ void finishTranslation(const Fault &fault, RequestPtr mem_req);
/** Check if an interrupt is pending and that we need to handle
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index fb933b8ca..b9e3b78c5 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -633,7 +633,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
template <class Impl>
void
-DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
+DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
{
ThreadID tid = mem_req->threadId();
Addr fetchBufferBlockPC = mem_req->getVaddr();