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-rw-r--r--src/cpu/o3/cpu.cc64
-rw-r--r--src/cpu/o3/cpu.hh35
-rw-r--r--src/cpu/o3/dyn_inst.hh25
-rw-r--r--src/cpu/o3/free_list.hh2
-rw-r--r--src/cpu/o3/regfile.hh96
-rw-r--r--src/cpu/o3/rename_impl.hh8
-rwxr-xr-xsrc/cpu/o3/thread_context.hh11
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh92
-rw-r--r--src/cpu/o3/thread_state.hh4
9 files changed, 45 insertions, 292 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 621b6c1b9..6722941e4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -361,7 +361,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
- tid, params->workload[tid], tid);
+ tid, params->workload[tid]);
//usedTids[tid] = true;
//threadMap[tid] = tid;
@@ -372,7 +372,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
- tid, dummy_proc, tid);
+ tid, dummy_proc);
//usedTids[tid] = false;
}
#endif // !FULL_SYSTEM
@@ -1180,14 +1180,14 @@ template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
- return this->regFile.readMiscRegNoEffect(misc_reg, tid);
+ return this->isa[tid].readMiscRegNoEffect(misc_reg);
}
template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
- return this->regFile.readMiscReg(misc_reg, tid);
+ return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
template <class Impl>
@@ -1195,7 +1195,7 @@ void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
- this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
+ this->isa[tid].setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
@@ -1203,7 +1203,7 @@ void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
- this->regFile.setMiscReg(misc_reg, val, tid);
+ this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
}
template <class Impl>
@@ -1215,13 +1215,6 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
template <class Impl>
FloatReg
-FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
-{
- return regFile.readFloatReg(reg_idx, width);
-}
-
-template <class Impl>
-FloatReg
FullO3CPU<Impl>::readFloatReg(int reg_idx)
{
return regFile.readFloatReg(reg_idx);
@@ -1229,13 +1222,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx)
template <class Impl>
FloatRegBits
-FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
-{
- return regFile.readFloatRegBits(reg_idx, width);
-}
-
-template <class Impl>
-FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
{
return regFile.readFloatRegBits(reg_idx);
@@ -1250,13 +1236,6 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
template <class Impl>
void
-FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
- regFile.setFloatReg(reg_idx, val, width);
-}
-
-template <class Impl>
-void
FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
regFile.setFloatReg(reg_idx, val);
@@ -1264,13 +1243,6 @@ FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-{
- regFile.setFloatRegBits(reg_idx, val, width);
-}
-
-template <class Impl>
-void
FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
regFile.setFloatRegBits(reg_idx, val);
@@ -1287,7 +1259,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
template <class Impl>
float
-FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
+FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1296,16 +1268,6 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
}
template <class Impl>
-double
-FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid)
-{
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
- return regFile.readFloatReg(phys_reg, 64);
-}
-
-template <class Impl>
uint64_t
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
{
@@ -1326,7 +1288,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1336,16 +1298,6 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid)
-{
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
- regFile.setFloatReg(phys_reg, val, 64);
-}
-
-template <class Impl>
-void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 5cf27df75..0cc8eab78 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -392,23 +392,6 @@ class FullO3CPU : public BaseO3CPU
/** Check if this address is a valid data address. */
bool validDataAddr(Addr addr) { return true; }
-
- /** Get instruction asid. */
- int getInstAsid(ThreadID tid)
- { return regFile.miscRegs[tid].getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(ThreadID tid)
- { return regFile.miscRegs[tid].getDataAsid(); }
-#else
- /** Get instruction asid. */
- int getInstAsid(ThreadID tid)
- { return thread[tid]->getInstAsid(); }
-
- /** Get data asid. */
- int getDataAsid(ThreadID tid)
- { return thread[tid]->getDataAsid(); }
-
#endif
/** Register accessors. Index refers to the physical register index. */
@@ -435,27 +418,17 @@ class FullO3CPU : public BaseO3CPU
TheISA::FloatReg readFloatReg(int reg_idx);
- TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
- TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
-
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
- void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
- void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
-
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
- float readArchFloatRegSingle(int reg_idx, ThreadID tid);
-
- double readArchFloatRegDouble(int reg_idx, ThreadID tid);
+ float readArchFloatReg(int reg_idx, ThreadID tid);
uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
@@ -466,9 +439,7 @@ class FullO3CPU : public BaseO3CPU
*/
void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
-
- void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
+ void setArchFloatReg(int reg_idx, float val, ThreadID tid);
void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
@@ -603,6 +574,8 @@ class FullO3CPU : public BaseO3CPU
/** Integer Register Scoreboard */
Scoreboard scoreboard;
+ TheISA::ISA isa[Impl::MaxThreads];
+
public:
/** Enum to give each stage a specific index, so when calling
* activateStage() or deactivateStage(), they can specify which stage
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 292547b6b..3ef42e91f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
- {
- return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
- }
-
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
- int width)
- {
- return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
- }
-
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
@@ -226,13 +215,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
- int width)
- {
- this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
- }
-
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
@@ -240,13 +222,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
}
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
- {
- this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
- }
-
- void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 79e10524b..e28c4910e 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -34,7 +34,7 @@
#include <iostream>
#include <queue>
-#include "arch/isa_traits.hh"
+#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 07f8d487b..d6beecdc5 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -33,7 +33,6 @@
#define __CPU_O3_REGFILE_HH__
#include "arch/isa_traits.hh"
-#include "arch/regfile.hh"
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
@@ -57,8 +56,6 @@ class PhysRegFile
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
- typedef TheISA::MiscReg MiscReg;
typedef union {
FloatReg d;
@@ -95,21 +92,6 @@ class PhysRegFile
return intRegFile[reg_idx];
}
- FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
- {
- // Remove the base Float reg dependency.
- reg_idx = reg_idx - numPhysicalIntRegs;
-
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
- FloatReg floatReg = floatRegFile[reg_idx].d;
-
- DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
- "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
-
- return floatReg;
- }
-
/** Reads a floating point register (double precision). */
FloatReg readFloatReg(PhysRegIndex reg_idx)
{
@@ -126,22 +108,6 @@ class PhysRegFile
return floatReg;
}
- /** Reads a floating point register as an integer. */
- FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
- {
- // Remove the base Float reg dependency.
- reg_idx = reg_idx - numPhysicalIntRegs;
-
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
- FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
-
- DPRINTF(IEW, "RegFile: Access to float register %i as int, "
- "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
-
- return floatRegBits;
- }
-
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
@@ -169,23 +135,6 @@ class PhysRegFile
intRegFile[reg_idx] = val;
}
- /** Sets a single precision floating point register to the given value. */
- void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
- {
- // Remove the base Float reg dependency.
- reg_idx = reg_idx - numPhysicalIntRegs;
-
- assert(reg_idx < numPhysicalFloatRegs);
-
- DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
- int(reg_idx), (uint64_t)val);
-
-#if THE_ISA == ALPHA_ISA
- if (reg_idx != TheISA::ZeroReg)
-#endif
- floatRegFile[reg_idx].d = val;
- }
-
/** Sets a double precision floating point register to the given value. */
void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{
@@ -203,20 +152,6 @@ class PhysRegFile
floatRegFile[reg_idx].d = val;
}
- /** Sets a floating point register to the given integer value. */
- void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
- {
- // Remove the base Float reg dependency.
- reg_idx = reg_idx - numPhysicalIntRegs;
-
- assert(reg_idx < numPhysicalFloatRegs);
-
- DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
- int(reg_idx), (uint64_t)val);
-
- floatRegFile[reg_idx].q = val;
- }
-
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
{
// Remove the base Float reg dependency.
@@ -230,30 +165,6 @@ class PhysRegFile
floatRegFile[reg_idx].q = val;
}
- MiscReg
- readMiscRegNoEffect(int misc_reg, ThreadID tid)
- {
- return miscRegs[tid].readRegNoEffect(misc_reg);
- }
-
- MiscReg
- readMiscReg(int misc_reg, ThreadID tid)
- {
- return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
- }
-
- void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
- {
- miscRegs[tid].setRegNoEffect(misc_reg, val);
- }
-
- void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
- {
- miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
- }
-
public:
/** (signed) integer register file. */
IntReg *intRegFile;
@@ -261,9 +172,6 @@ class PhysRegFile
/** Floating point register file. */
PhysFloatReg *floatRegFile;
- /** Miscellaneous register file. */
- MiscRegFile miscRegs[Impl::MaxThreads];
-
#if FULL_SYSTEM
private:
int intrflag; // interrupt flag
@@ -289,10 +197,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
intRegFile = new IntReg[numPhysicalIntRegs];
floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
- for (int i = 0; i < Impl::MaxThreads; ++i) {
- miscRegs[i].clear();
- }
-
memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
}
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 2bca6f81c..e4cc2674b 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -32,7 +32,7 @@
#include <list>
#include "arch/isa_traits.hh"
-#include "arch/regfile.hh"
+#include "arch/registers.hh"
#include "config/full_system.hh"
#include "cpu/o3/rename.hh"
#include "params/DerivO3CPU.hh"
@@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
RegIndex src_reg = inst->srcRegIdx(src_idx);
RegIndex flat_src_reg = src_reg;
if (src_reg < TheISA::FP_Base_DepTag) {
- flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
+ flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
} else if (src_reg < TheISA::Ctrl_Base_DepTag) {
src_reg = src_reg - TheISA::FP_Base_DepTag;
- flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
+ flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
flat_src_reg += TheISA::NumIntRegs;
} else {
flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
@@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
RegIndex flat_dest_reg = dest_reg;
if (dest_reg < TheISA::FP_Base_DepTag) {
// Integer registers are flattened.
- flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
+ flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
} else {
// Floating point and Miscellaneous registers need their indexes
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b10305d5d..ed5c6ac20 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext
/** Reads an integer register. */
virtual uint64_t readIntReg(int reg_idx);
- virtual FloatReg readFloatReg(int reg_idx, int width);
-
virtual FloatReg readFloatReg(int reg_idx);
- virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
virtual FloatRegBits readFloatRegBits(int reg_idx);
/** Sets an integer register to a value. */
virtual void setIntReg(int reg_idx, uint64_t val);
- virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
virtual void setFloatReg(int reg_idx, FloatReg val);
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
/** Reads this thread's PC. */
@@ -226,6 +218,9 @@ class O3ThreadContext : public ThreadContext
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual int flattenIntIndex(int reg);
+ virtual int flattenFloatIndex(int reg);
+
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
virtual unsigned readStCondFailures()
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index bce334dc4..e631c9244 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -29,7 +29,7 @@
* Korey Sewell
*/
-#include "arch/regfile.hh"
+#include "arch/registers.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
@@ -272,48 +272,23 @@ template <class Impl>
uint64_t
O3ThreadContext<Impl>::readIntReg(int reg_idx)
{
- reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
return cpu->readArchIntReg(reg_idx, thread->threadId());
}
template <class Impl>
TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
-{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- switch(width) {
- case 32:
- return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
- case 64:
- return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
- default:
- panic("Unsupported width!");
- return 0;
- }
-}
-
-template <class Impl>
-TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
-}
-
-template <class Impl>
-TheISA::FloatRegBits
-O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
-{
- DPRINTF(Fault, "Reading floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+ return cpu->readArchFloatReg(reg_idx, thread->threadId());
}
template <class Impl>
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
}
@@ -321,7 +296,7 @@ template <class Impl>
void
O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
{
- reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
cpu->setArchIntReg(reg_idx, val, thread->threadId());
// Squash if we're not already in a state update mode.
@@ -332,30 +307,10 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- switch(width) {
- case 32:
- cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
- break;
- case 64:
- cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
- break;
- }
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
-}
-
-template <class Impl>
-void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+ cpu->setArchFloatReg(reg_idx, val, thread->threadId());
if (!thread->trapPending && !thread->inSyscall) {
cpu->squashFromTC(thread->threadId());
@@ -364,24 +319,9 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
- int width)
-{
- DPRINTF(Fault, "Setting floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
- cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
-}
-
-template <class Impl>
-void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
// Squash if we're not already in a state update mode.
@@ -439,6 +379,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
}
template <class Impl>
+int
+O3ThreadContext<Impl>::flattenIntIndex(int reg)
+{
+ return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+}
+
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenFloatIndex(int reg)
+{
+ return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+}
+
+template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1f0e7a3bb..1171053b9 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState {
profilePC = 3;
}
#else
- O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
- : ThreadState(_cpu, _thread_num, _process, _asid),
+ O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
+ : ThreadState(_cpu, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0)
{ }
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 19:00:46 +0000