4 files changed, 0 insertions, 51 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 70417d51f..ba6e80ff2 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -918,24 +918,6 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
 }
 
 template <class Impl>
-Fault
-FullO3CPU<Impl>::hwrei(ThreadID tid)
-{
-#if THE_ISA == ALPHA_ISA
-    // Need to clear the lock flag upon returning from an interrupt.
-    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
-
-    auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
-            this->thread[tid]->kernelStats);
-    assert(stats);
-    stats->hwrei();
-
-    // FIXME: XXX check for interrupts? XXX
-#endif
-    return NoFault;
-}
-
-template <class Impl>
 bool
 FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c2c48535f..bd1479acc 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -385,9 +385,6 @@ class FullO3CPU : public BaseO3CPU
     /** Traps to handle given fault. */
     void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
 
-    /** HW return from error interrupt. */
-    Fault hwrei(ThreadID tid);
-
     bool simPalCheck(int palFunc, ThreadID tid);
 
     /** Check if a change in renaming is needed for vector registers.
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 01886606e..9b6c1fbb8 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -248,8 +248,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
             }
         }
     }
-    /** Calls hardware return from error interrupt. */
-    Fault hwrei() override;
     /** Traps to handle specified fault. */
     void trap(const Fault &fault);
     bool simPalCheck(int palFunc) override;
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 03437a5ae..5fb597379 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -185,34 +185,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
 }
 
 template <class Impl>
-Fault
-BaseO3DynInst<Impl>::hwrei()
-{
-#if THE_ISA == ALPHA_ISA
-    // Can only do a hwrei when in pal mode.
-    if (!(this->instAddr() & 0x3))
-        return std::make_shared<AlphaISA::UnimplementedOpcodeFault>();
-
-    // Set the next PC based on the value of the EXC_ADDR IPR.
-    AlphaISA::PCState pc = this->pcState();
-    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
-                                          this->threadNumber));
-    this->pcState(pc);
-    if (CPA::available()) {
-        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
-        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
-    }
-
-    // Tell CPU to clear any state it needs to if a hwrei is taken.
-    this->cpu->hwrei(this->threadNumber);
-#else
-
-#endif
-    // FIXME: XXX check for interrupts? XXX
-    return NoFault;
-}
-
-template <class Impl>
 void
 BaseO3DynInst<Impl>::trap(const Fault &fault)
 {