diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/thread_context.hh | 299 | ||||
| -rw-r--r-- | src/cpu/o3/thread_context_impl.hh | 37 |
2 files changed, 192 insertions, 144 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 374ef377d..b87aac4a7 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -99,115 +99,121 @@ class O3ThreadContext : public ThreadContext } /** Returns a pointer to this CPU. */ - virtual BaseCPU *getCpuPtr() override { return cpu; } + BaseCPU *getCpuPtr() override { return cpu; } /** Reads this CPU's ID. */ - virtual int cpuId() const override { return cpu->cpuId(); } + int cpuId() const override { return cpu->cpuId(); } /** Reads this CPU's Socket ID. */ - virtual uint32_t socketId() const override { return cpu->socketId(); } + uint32_t socketId() const override { return cpu->socketId(); } - virtual ContextID - contextId() const override { return thread->contextId(); } + ContextID contextId() const override { return thread->contextId(); } - virtual void setContextId(int id) override { thread->setContextId(id); } + void setContextId(ContextID id) override { thread->setContextId(id); } /** Returns this thread's ID number. */ - virtual int threadId() const override - { return thread->threadId(); } - virtual void setThreadId(int id) override - { return thread->setThreadId(id); } + int threadId() const override { return thread->threadId(); } + void setThreadId(int id) override { return thread->setThreadId(id); } /** Returns a pointer to the system. */ - virtual System *getSystemPtr() override { return cpu->system; } + System *getSystemPtr() override { return cpu->system; } /** Returns a pointer to this thread's kernel statistics. */ - virtual TheISA::Kernel::Statistics *getKernelStats() override - { return thread->kernelStats; } + TheISA::Kernel::Statistics * + getKernelStats() override + { + return thread->kernelStats; + } /** Returns a pointer to this thread's process. */ - virtual Process *getProcessPtr() override - { return thread->getProcessPtr(); } + Process *getProcessPtr() override { return thread->getProcessPtr(); } - virtual void setProcessPtr(Process *p) override - { thread->setProcessPtr(p); } + void setProcessPtr(Process *p) override { thread->setProcessPtr(p); } - virtual PortProxy &getPhysProxy() override - { return thread->getPhysProxy(); } + PortProxy &getPhysProxy() override { return thread->getPhysProxy(); } - virtual FSTranslatingPortProxy &getVirtProxy() override; + FSTranslatingPortProxy &getVirtProxy() override; - virtual void initMemProxies(ThreadContext *tc) override - { thread->initMemProxies(tc); } + void + initMemProxies(ThreadContext *tc) override + { + thread->initMemProxies(tc); + } - virtual SETranslatingPortProxy &getMemProxy() override - { return thread->getMemProxy(); } + SETranslatingPortProxy & + getMemProxy() override + { + return thread->getMemProxy(); + } /** Returns this thread's status. */ - virtual Status status() const override { return thread->status(); } + Status status() const override { return thread->status(); } /** Sets this thread's status. */ - virtual void setStatus(Status new_status) override - { thread->setStatus(new_status); } + void + setStatus(Status new_status) override + { + thread->setStatus(new_status); + } /** Set the status to Active. */ - virtual void activate() override; + void activate() override; /** Set the status to Suspended. */ - virtual void suspend() override; + void suspend() override; /** Set the status to Halted. */ - virtual void halt() override; + void halt() override; /** Dumps the function profiling information. * @todo: Implement. */ - virtual void dumpFuncProfile() override; + void dumpFuncProfile() override; /** Takes over execution of a thread from another CPU. */ - virtual void takeOverFrom(ThreadContext *old_context) override; + void takeOverFrom(ThreadContext *old_context) override; /** Registers statistics associated with this TC. */ - virtual void regStats(const std::string &name) override; + void regStats(const std::string &name) override; /** Reads the last tick that this thread was activated on. */ - virtual Tick readLastActivate() override; + Tick readLastActivate() override; /** Reads the last tick that this thread was suspended on. */ - virtual Tick readLastSuspend() override; + Tick readLastSuspend() override; /** Clears the function profiling information. */ - virtual void profileClear() override; + void profileClear() override; /** Samples the function profiling information. */ - virtual void profileSample() override; + void profileSample() override; /** Copies the architectural registers from another TC into this TC. */ - virtual void copyArchRegs(ThreadContext *tc) override; + void copyArchRegs(ThreadContext *tc) override; /** Resets all architectural registers to 0. */ - virtual void clearArchRegs() override; + void clearArchRegs() override; /** Reads an integer register. */ - virtual RegVal - readReg(int reg_idx) + RegVal + readReg(RegIndex reg_idx) { return readIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index()); } - virtual RegVal - readIntReg(int reg_idx) override + RegVal + readIntReg(RegIndex reg_idx) const override { return readIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index()); } - virtual RegVal - readFloatReg(int reg_idx) override + RegVal + readFloatReg(RegIndex reg_idx) const override { return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index()); } - virtual const VecRegContainer & + const VecRegContainer & readVecReg(const RegId& id) const override { return readVecRegFlat(flattenRegId(id).index()); @@ -216,7 +222,7 @@ class O3ThreadContext : public ThreadContext /** * Read vector register operand for modification, hierarchical indexing. */ - virtual VecRegContainer & + VecRegContainer & getWritableVecReg(const RegId& id) override { return getWritableVecRegFlat(flattenRegId(id).index()); @@ -225,7 +231,7 @@ class O3ThreadContext : public ThreadContext /** Vector Register Lane Interfaces. */ /** @{ */ /** Reads source vector 8bit operand. */ - virtual ConstVecLane8 + ConstVecLane8 readVec8BitLaneReg(const RegId& id) const override { return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), @@ -233,7 +239,7 @@ class O3ThreadContext : public ThreadContext } /** Reads source vector 16bit operand. */ - virtual ConstVecLane16 + ConstVecLane16 readVec16BitLaneReg(const RegId& id) const override { return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), @@ -241,7 +247,7 @@ class O3ThreadContext : public ThreadContext } /** Reads source vector 32bit operand. */ - virtual ConstVecLane32 + ConstVecLane32 readVec32BitLaneReg(const RegId& id) const override { return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), @@ -249,7 +255,7 @@ class O3ThreadContext : public ThreadContext } /** Reads source vector 64bit operand. */ - virtual ConstVecLane64 + ConstVecLane64 readVec64BitLaneReg(const RegId& id) const override { return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), @@ -257,137 +263,180 @@ class O3ThreadContext : public ThreadContext } /** Write a lane of the destination vector register. */ - virtual void setVecLane(const RegId& reg, - const LaneData<LaneSize::Byte>& val) override - { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } - virtual void setVecLane(const RegId& reg, - const LaneData<LaneSize::TwoByte>& val) override - { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } - virtual void setVecLane(const RegId& reg, - const LaneData<LaneSize::FourByte>& val) override - { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } - virtual void setVecLane(const RegId& reg, - const LaneData<LaneSize::EightByte>& val) override - { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } + void + setVecLane(const RegId& reg, + const LaneData<LaneSize::Byte>& val) override + { + return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); + } + void + setVecLane(const RegId& reg, + const LaneData<LaneSize::TwoByte>& val) override + { + return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); + } + void + setVecLane(const RegId& reg, + const LaneData<LaneSize::FourByte>& val) override + { + return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); + } + void + setVecLane(const RegId& reg, + const LaneData<LaneSize::EightByte>& val) override + { + return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); + } /** @} */ - virtual const VecElem& readVecElem(const RegId& reg) const override { + const VecElem & + readVecElem(const RegId& reg) const override + { return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); } - virtual const VecPredRegContainer& - readVecPredReg(const RegId& id) const override { + const VecPredRegContainer & + readVecPredReg(const RegId& id) const override + { return readVecPredRegFlat(flattenRegId(id).index()); } - virtual VecPredRegContainer& - getWritableVecPredReg(const RegId& id) override { + VecPredRegContainer& + getWritableVecPredReg(const RegId& id) override + { return getWritableVecPredRegFlat(flattenRegId(id).index()); } - virtual RegVal - readCCReg(int reg_idx) override + RegVal + readCCReg(RegIndex reg_idx) const override { return readCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index()); } /** Sets an integer register to a value. */ - virtual void - setIntReg(int reg_idx, RegVal val) override + void + setIntReg(RegIndex reg_idx, RegVal val) override { setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); } - virtual void - setFloatReg(int reg_idx, RegVal val) override + void + setFloatReg(RegIndex reg_idx, RegVal val) override { setFloatRegFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index(), val); } - virtual void + void setVecReg(const RegId& reg, const VecRegContainer& val) override { setVecRegFlat(flattenRegId(reg).index(), val); } - virtual void + void setVecElem(const RegId& reg, const VecElem& val) override { setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } - virtual void + void setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override { setVecPredRegFlat(flattenRegId(reg).index(), val); } - virtual void - setCCReg(int reg_idx, RegVal val) override + void + setCCReg(RegIndex reg_idx, RegVal val) override { setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); } /** Reads this thread's PC state. */ - virtual TheISA::PCState pcState() override - { return cpu->pcState(thread->threadId()); } + TheISA::PCState + pcState() const override + { + return cpu->pcState(thread->threadId()); + } /** Sets this thread's PC state. */ - virtual void pcState(const TheISA::PCState &val) override; + void pcState(const TheISA::PCState &val) override; - virtual void pcStateNoRecord(const TheISA::PCState &val) override; + void pcStateNoRecord(const TheISA::PCState &val) override; /** Reads this thread's PC. */ - virtual Addr instAddr() override - { return cpu->instAddr(thread->threadId()); } + Addr + instAddr() const override + { + return cpu->instAddr(thread->threadId()); + } /** Reads this thread's next PC. */ - virtual Addr nextInstAddr() override - { return cpu->nextInstAddr(thread->threadId()); } + Addr + nextInstAddr() const override + { + return cpu->nextInstAddr(thread->threadId()); + } /** Reads this thread's next PC. */ - virtual MicroPC microPC() override - { return cpu->microPC(thread->threadId()); } + MicroPC + microPC() const override + { + return cpu->microPC(thread->threadId()); + } /** Reads a miscellaneous register. */ - virtual RegVal readMiscRegNoEffect(int misc_reg) const override - { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } + RegVal + readMiscRegNoEffect(RegIndex misc_reg) const override + { + return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); + } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual RegVal readMiscReg(int misc_reg) override - { return cpu->readMiscReg(misc_reg, thread->threadId()); } + RegVal + readMiscReg(RegIndex misc_reg) override + { + return cpu->readMiscReg(misc_reg, thread->threadId()); + } /** Sets a misc. register. */ - virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; + void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override; /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscReg(int misc_reg, RegVal val) override; + void setMiscReg(RegIndex misc_reg, RegVal val) override; - virtual RegId flattenRegId(const RegId& regId) const override; + RegId flattenRegId(const RegId& regId) const override; /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. - virtual unsigned readStCondFailures() override - { return thread->storeCondFailures; } + unsigned + readStCondFailures() const override + { + return thread->storeCondFailures; + } /** Sets the number of consecutive store conditional failures. */ - virtual void setStCondFailures(unsigned sc_failures) override - { thread->storeCondFailures = sc_failures; } + void + setStCondFailures(unsigned sc_failures) override + { + thread->storeCondFailures = sc_failures; + } /** Executes a syscall in SE mode. */ - virtual void syscall(int64_t callnum, Fault *fault) override - { return cpu->syscall(callnum, thread->threadId(), fault); } + void + syscall(int64_t callnum, Fault *fault) override + { + return cpu->syscall(callnum, thread->threadId(), fault); + } /** Reads the funcExeInst counter. */ - virtual Counter readFuncExeInst() override { return thread->funcExeInst; } + Counter readFuncExeInst() const override { return thread->funcExeInst; } /** Returns pointer to the quiesce event. */ - virtual EndQuiesceEvent * + EndQuiesceEvent * getQuiesceEvent() override { return this->thread->quiesceEvent; @@ -404,46 +453,44 @@ class O3ThreadContext : public ThreadContext cpu->squashFromTC(thread->threadId()); } - virtual RegVal readIntRegFlat(int idx) override; - virtual void setIntRegFlat(int idx, RegVal val) override; + RegVal readIntRegFlat(RegIndex idx) const override; + void setIntRegFlat(RegIndex idx, RegVal val) override; - virtual RegVal readFloatRegFlat(int idx) override; - virtual void setFloatRegFlat(int idx, RegVal val) override; + RegVal readFloatRegFlat(RegIndex idx) const override; + void setFloatRegFlat(RegIndex idx, RegVal val) override; - virtual const VecRegContainer& readVecRegFlat(int idx) const override; + const VecRegContainer& readVecRegFlat(RegIndex idx) const override; /** Read vector register operand for modification, flat indexing. */ - virtual VecRegContainer& getWritableVecRegFlat(int idx) override; - virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; + VecRegContainer& getWritableVecRegFlat(RegIndex idx) override; + void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override; template <typename VecElem> VecLaneT<VecElem, true> - readVecLaneFlat(int idx, int lId) const + readVecLaneFlat(RegIndex idx, int lId) const { return cpu->template readArchVecLane<VecElem>(idx, lId, thread->threadId()); } template <typename LD> - void setVecLaneFlat(int idx, int lId, const LD& val) + void + setVecLaneFlat(int idx, int lId, const LD& val) { cpu->template setArchVecLane(idx, lId, thread->threadId(), val); } - virtual const VecElem& readVecElemFlat( - const RegIndex& idx, - const ElemIndex& elemIndex) const override; - virtual void setVecElemFlat( - const RegIndex& idx, - const ElemIndex& elemIdx, const VecElem& val) override; + const VecElem &readVecElemFlat(RegIndex idx, + const ElemIndex& elemIndex) const override; + void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, + const VecElem& val) override; - virtual const VecPredRegContainer& readVecPredRegFlat(int idx) - const override; - virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; - virtual void setVecPredRegFlat(int idx, - const VecPredRegContainer& val) override; + const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override; + VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override; + void setVecPredRegFlat(RegIndex idx, + const VecPredRegContainer& val) override; - virtual RegVal readCCRegFlat(int idx) override; - virtual void setCCRegFlat(int idx, RegVal val) override; + RegVal readCCRegFlat(RegIndex idx) const override; + void setCCRegFlat(RegIndex idx, RegVal val) override; }; #endif diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 57e0a45f5..58dee9814 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -205,64 +205,64 @@ O3ThreadContext<Impl>::clearArchRegs() template <class Impl> RegVal -O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) +O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const { return cpu->readArchIntReg(reg_idx, thread->threadId()); } template <class Impl> RegVal -O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) +O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const { return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template <class Impl> const TheISA::VecRegContainer& -O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const +O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const { return cpu->readArchVecReg(reg_id, thread->threadId()); } template <class Impl> TheISA::VecRegContainer& -O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id) +O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id) { return cpu->getWritableArchVecReg(reg_id, thread->threadId()); } template <class Impl> const TheISA::VecElem& -O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx, - const ElemIndex& elemIndex) const +O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx, + const ElemIndex& elemIndex) const { return cpu->readArchVecElem(idx, elemIndex, thread->threadId()); } template <class Impl> const TheISA::VecPredRegContainer& -O3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const +O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const { return cpu->readArchVecPredReg(reg_id, thread->threadId()); } template <class Impl> TheISA::VecPredRegContainer& -O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id) +O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id) { return cpu->getWritableArchVecPredReg(reg_id, thread->threadId()); } template <class Impl> RegVal -O3ThreadContext<Impl>::readCCRegFlat(int reg_idx) +O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const { return cpu->readArchCCReg(reg_idx, thread->threadId()); } template <class Impl> void -O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) +O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val) { cpu->setArchIntReg(reg_idx, val, thread->threadId()); @@ -271,7 +271,7 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val) +O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val) { cpu->setArchFloatReg(reg_idx, val, thread->threadId()); @@ -280,7 +280,8 @@ O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val) template <class Impl> void -O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val) +O3ThreadContext<Impl>::setVecRegFlat( + RegIndex reg_idx, const VecRegContainer& val) { cpu->setArchVecReg(reg_idx, val, thread->threadId()); @@ -289,7 +290,7 @@ O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val) template <class Impl> void -O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx, +O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx, const ElemIndex& elemIndex, const VecElem& val) { cpu->setArchVecElem(idx, elemIndex, val, thread->threadId()); @@ -298,7 +299,7 @@ O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx, template <class Impl> void -O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx, +O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx, const VecPredRegContainer& val) { cpu->setArchVecPredReg(reg_idx, val, thread->threadId()); @@ -308,7 +309,7 @@ O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx, template <class Impl> void -O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val) +O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val) { cpu->setArchCCReg(reg_idx, val, thread->threadId()); @@ -342,20 +343,20 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const template <class Impl> void -O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val) +O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) { cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); conditionalSquash(); } -#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ template <class Impl> void -O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val) +O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val) { cpu->setMiscReg(misc_reg, val, thread->threadId()); conditionalSquash(); } +#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__ |