diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/FUPool.py | 14 | ||||
| -rw-r--r-- | src/cpu/o3/FuncUnitConfig.py | 14 |
2 files changed, 25 insertions, 3 deletions
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py index 1461b405c..55fb82f84 100644 --- a/src/cpu/o3/FUPool.py +++ b/src/cpu/o3/FUPool.py @@ -1,3 +1,15 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -38,4 +50,4 @@ class FUPool(SimObject): class DefaultFUPool(FUPool): FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] + SIMD_Unit(), PredALU(), WritePort(), RdWrPort(), IprPort() ] diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index ef114df09..3b02aab79 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010, 2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -86,6 +86,7 @@ class SIMD_Unit(FUDesc): OpDesc(opClass='SimdMultAcc'), OpDesc(opClass='SimdShift'), OpDesc(opClass='SimdShiftAcc'), + OpDesc(opClass='SimdDiv'), OpDesc(opClass='SimdSqrt'), OpDesc(opClass='SimdFloatAdd'), OpDesc(opClass='SimdFloatAlu'), @@ -95,9 +96,18 @@ class SIMD_Unit(FUDesc): OpDesc(opClass='SimdFloatMisc'), OpDesc(opClass='SimdFloatMult'), OpDesc(opClass='SimdFloatMultAcc'), - OpDesc(opClass='SimdFloatSqrt') ] + OpDesc(opClass='SimdFloatSqrt'), + OpDesc(opClass='SimdReduceAdd'), + OpDesc(opClass='SimdReduceAlu'), + OpDesc(opClass='SimdReduceCmp'), + OpDesc(opClass='SimdFloatReduceAdd'), + OpDesc(opClass='SimdFloatReduceCmp') ] count = 4 +class PredALU(FUDesc): + opList = [ OpDesc(opClass='SimdPredAlu') ] + count = 1 + class ReadPort(FUDesc): opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='FloatMemRead') ] |