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-rw-r--r--src/cpu/ozone/cpu.hh79
1 files changed, 36 insertions, 43 deletions
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index e9550c39b..e411c12bd 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -43,6 +43,7 @@
#include "cpu/ozone/thread_state.hh"
#include "cpu/pc_event.hh"
#include "cpu/static_inst.hh"
+#include "mem/page_table.hh"
#include "sim/eventq.hh"
// forward declarations
@@ -54,7 +55,6 @@ class AlphaDTB;
class PhysicalMemory;
class MemoryController;
-class Sampler;
class RemoteGDB;
class GDBListener;
@@ -70,6 +70,7 @@ class Process;
class Checkpoint;
class EndQuiesceEvent;
+class MemObject;
class Request;
namespace Trace {
@@ -111,7 +112,7 @@ class OzoneCPU : public BaseCPU
void setCpuId(int id);
- int readCpuId() { return thread->cpuId; }
+ int readCpuId() { return thread->readCpuId(); }
#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; }
@@ -122,22 +123,22 @@ class OzoneCPU : public BaseCPU
AlphaDTB * getDTBPtr() { return cpu->dtb; }
- Kernel::Statistics *getKernelStats() { return thread->kernelStats; }
+ Kernel::Statistics *getKernelStats()
+ { return thread->getKernelStats(); }
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
VirtualPort *getVirtPort(ThreadContext *tc = NULL)
{ return thread->getVirtPort(tc); }
- void delVirtPort(VirtualPort *vp)
- { thread->delVirtPort(vp); }
+ void delVirtPort(VirtualPort *vp);
#else
- TranslatingPort *getMemPort() { return thread->port; }
+ TranslatingPort *getMemPort() { return thread->getMemPort(); }
- Process *getProcessPtr() { return thread->process; }
+ Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
- Status status() const { return thread->_status; }
+ Status status() const { return thread->status(); }
void setStatus(Status new_status);
@@ -149,7 +150,7 @@ class OzoneCPU : public BaseCPU
void suspend();
/// Set the status to Unallocated.
- void deallocate();
+ void deallocate(int delay = 0);
/// Set the status to Halted.
void halt();
@@ -212,12 +213,11 @@ class OzoneCPU : public BaseCPU
uint64_t readNextNPC()
{
- panic("Alpha has no NextNPC!");
return 0;
}
void setNextNPC(uint64_t val)
- { panic("Alpha has no NextNPC!"); }
+ { }
public:
// ISA stuff:
@@ -250,7 +250,7 @@ class OzoneCPU : public BaseCPU
{ thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
void setSyscallReturn(SyscallReturn return_value)
- { cpu->setSyscallReturn(return_value, thread->tid); }
+ { cpu->setSyscallReturn(return_value, thread->readTid()); }
Counter readFuncExeInst() { return thread->funcExeInst; }
@@ -355,12 +355,10 @@ class OzoneCPU : public BaseCPU
int cpuId;
- void switchOut(Sampler *sampler);
+ void switchOut();
void signalSwitched();
void takeOverFrom(BaseCPU *oldCPU);
- Sampler *sampler;
-
int switchCount;
#if FULL_SYSTEM
@@ -374,6 +372,10 @@ class OzoneCPU : public BaseCPU
PhysicalMemory *physmem;
#endif
+ virtual Port *getPort(const std::string &name, int idx);
+
+ MemObject *mem;
+
FrontEnd *frontEnd;
BackEnd *backEnd;
@@ -383,7 +385,7 @@ class OzoneCPU : public BaseCPU
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
- virtual void deallocateContext(int thread_num);
+ virtual void deallocateContext(int thread_num, int delay);
virtual void haltContext(int thread_num);
// statistics
@@ -415,50 +417,41 @@ class OzoneCPU : public BaseCPU
#if FULL_SYSTEM
- bool validInstAddr(Addr addr) { return true; }
- bool validDataAddr(Addr addr) { return true; }
-
- Fault translateInstReq(Request *req)
+ /** Translates instruction requestion. */
+ Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return itb->translate(req, tc);
+ return itb->translate(req, thread->getTC());
}
- Fault translateDataReadReq(Request *req)
+ /** Translates data read request. */
+ Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return dtb->translate(req, tc, false);
+ return dtb->translate(req, thread->getTC(), false);
}
- Fault translateDataWriteReq(Request *req)
+ /** Translates data write request. */
+ Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return dtb->translate(req, tc, true);
+ return dtb->translate(req, thread->getTC(), true);
}
#else
- bool validInstAddr(Addr addr)
- { return true; }
-
- bool validDataAddr(Addr addr)
- { return true; }
-
- int getInstAsid() { return thread.asid; }
- int getDataAsid() { return thread.asid; }
-
/** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(Request *req)
+ Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return thread.translateInstReq(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(Request *req)
+ Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return thread.translateDataReadReq(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(Request *req)
+ Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
{
- return thread.translateDataWriteReq(req);
+ return thread->getProcessPtr()->pTable->translate(req);
}
#endif
@@ -599,14 +592,14 @@ class OzoneCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei();
- int readIntrFlag() { return thread.regs.intrflag; }
- void setIntrFlag(int val) { thread.regs.intrflag = val; }
+ int readIntrFlag() { return thread.intrflag; }
+ void setIntrFlag(int val) { thread.intrflag = val; }
bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
bool simPalCheck(int palFunc);
void processInterrupts();
#else
- void syscall();
+ void syscall(uint64_t &callnum);
void setSyscallReturn(SyscallReturn return_value, int tid);
#endif