summaryrefslogtreecommitdiff
path: root/src/cpu/ozone
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r--src/cpu/ozone/back_end.hh10
-rw-r--r--src/cpu/ozone/cpu_impl.hh2
-rw-r--r--src/cpu/ozone/front_end.hh2
-rw-r--r--src/cpu/ozone/inorder_back_end.hh10
-rw-r--r--src/cpu/ozone/lsq_unit_impl.hh2
-rw-r--r--src/cpu/ozone/lw_back_end.hh2
6 files changed, 14 insertions, 14 deletions
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 4cdc86c3c..84429f3c1 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -447,7 +447,7 @@ class BackEnd
Stats::Scalar<> ROB_fcount;
Stats::Formula ROB_full_rate;
- Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Vector<> ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
Stats::VectorDistribution<> ROB_occ_dist;
public:
@@ -482,8 +482,8 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
} else {
// do functional access
@@ -524,8 +524,8 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
}
}
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index ec531d571..ceb980d4c 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -585,7 +585,7 @@ OzoneCPU<Impl>::post_interrupt(int int_num, int index)
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
-// thread.activate();
+// thread.activate();
// Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call.
activateContext(thread.readTid(), 1);
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 667392c06..fac243449 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -307,7 +307,7 @@ class FrontEnd
Stats::Formula idleRate;
Stats::Formula branchRate;
Stats::Formula fetchRate;
- Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
+ Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
Stats::Formula IFQOccupancy;
Stats::Formula IFQLatency;
Stats::Scalar<> IFQFcount; // cumulative IFQ full count
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index aef29b1e2..c23d801ba 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -222,7 +222,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
// are executed twice.
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -249,7 +249,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;
-// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
+// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->flags &= ~INST_READ;
@@ -261,7 +261,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (result != MA_HIT) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -307,7 +307,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss load stall!\n");
} else {
@@ -372,7 +372,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss store stall!\n");
} else {
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index 84a90eede..c24410520 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -553,7 +553,7 @@ OzoneLSQ<Impl>::writebackStores()
MemReqPtr req = storeQueue[storeWBIdx].req;
storeQueue[storeWBIdx].committed = true;
-// Fault fault = cpu->translateDataReadReq(req);
+// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Write;
req->completionEvent = NULL;
req->time = curTick;
diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index a335ab7dc..8ab50d5c9 100644
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -407,7 +407,7 @@ class LWBackEnd
Stats::Scalar<> ROBFcount;
Stats::Formula ROBFullRate;
- Stats::Vector<> ROBCount; // cumulative ROB occupancy
+ Stats::Vector<> ROBCount; // cumulative ROB occupancy
Stats::Formula ROBOccRate;
// Stats::VectorDistribution<> ROBOccDist;
public: