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-rw-r--r--src/cpu/ozone/cpu.hh47
-rw-r--r--src/cpu/ozone/front_end_impl.hh2
-rw-r--r--src/cpu/ozone/inorder_back_end.hh4
3 files changed, 7 insertions, 46 deletions
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 55ad7b3fb..0eb4b31f7 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -415,59 +415,20 @@ class OzoneCPU : public BaseCPU
void demapPage(Addr vaddr, uint64_t asn)
{
- itb->demap(vaddr, asn);
- dtb->demap(vaddr, asn);
+ cpu->itb->demap(vaddr, asn);
+ cpu->dtb->demap(vaddr, asn);
}
void demapInstPage(Addr vaddr, uint64_t asn)
{
- itb->demap(vaddr, asn);
+ cpu->itb->demap(vaddr, asn);
}
void demapDataPage(Addr vaddr, uint64_t asn)
{
- dtb->demap(vaddr, asn);
+ cpu->dtb->demap(vaddr, asn);
}
-#if FULL_SYSTEM
- /** Translates instruction requestion. */
- Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return itb->translate(req, thread->getTC());
- }
-
- /** Translates data read request. */
- Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return dtb->translate(req, thread->getTC(), false);
- }
-
- /** Translates data write request. */
- Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return dtb->translate(req, thread->getTC(), true);
- }
-
-#else
- /** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
- /** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
- /** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-#endif
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(Request *req, T &data, int load_idx)
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index b1e131115..2a9b107d4 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
PC, cpu->thread->contextId());
// Translate the instruction request.
- fault = cpu->translateInstReq(memReq, thread);
+ fault = cpu->itb->translate(memReq, thread);
// Now do the timing access to see whether or not the instruction
// exists within the cache.
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index c23d801ba..8850fa737 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault fault = cpu->translateDataReadReq(memReq);
+ Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false);
// if we have a cache, do cache access too
if (fault == NoFault && dcacheInterface) {
@@ -245,7 +245,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault fault = cpu->translateDataWriteReq(memReq);
+ Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true);
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;