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-rw-r--r--src/cpu/ozone/checker_builder.cc4
-rw-r--r--src/cpu/ozone/cpu.hh39
-rw-r--r--src/cpu/ozone/cpu_builder.cc9
-rw-r--r--src/cpu/ozone/cpu_impl.hh45
-rw-r--r--src/cpu/ozone/dyn_inst.hh9
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh38
-rw-r--r--src/cpu/ozone/front_end.hh2
-rw-r--r--src/cpu/ozone/front_end_impl.hh14
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh6
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh3
-rw-r--r--src/cpu/ozone/lw_lsq.hh2
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh2
-rw-r--r--src/cpu/ozone/simple_cpu_builder.cc4
-rw-r--r--src/cpu/ozone/simple_params.hh11
-rw-r--r--src/cpu/ozone/thread_state.hh18
15 files changed, 74 insertions, 132 deletions
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index b4c4686b7..9ad1e639f 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
Param<Tick> progress_interval;
#if FULL_SYSTEM
- SimObjectParam<AlphaITB *> itb;
- SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<TheISA::ITB *> itb;
+ SimObjectParam<TheISA::DTB *> dtb;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 70ec1d101..c1373944d 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -51,16 +51,21 @@
#if FULL_SYSTEM
#include "arch/alpha/tlb.hh"
-class AlphaITB;
-class AlphaDTB;
+namespace TheISA
+{
+ class ITB;
+ class DTB;
+}
class PhysicalMemory;
class MemoryController;
class RemoteGDB;
class GDBListener;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
};
#else
@@ -120,11 +125,11 @@ class OzoneCPU : public BaseCPU
PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
- AlphaITB *getITBPtr() { return cpu->itb; }
+ TheISA::ITB *getITBPtr() { return cpu->itb; }
- AlphaDTB * getDTBPtr() { return cpu->dtb; }
+ TheISA::DTB * getDTBPtr() { return cpu->dtb; }
- Kernel::Statistics *getKernelStats()
+ TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
@@ -224,11 +229,11 @@ class OzoneCPU : public BaseCPU
// ISA stuff:
MiscReg readMiscReg(int misc_reg);
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+ MiscReg readMiscRegWithEffect(int misc_reg);
- Fault setMiscReg(int misc_reg, const MiscReg &val);
+ void setMiscReg(int misc_reg, const MiscReg &val);
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+ void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
unsigned readStCondFailures()
{ return thread->storeCondFailures; }
@@ -236,10 +241,6 @@ class OzoneCPU : public BaseCPU
void setStCondFailures(unsigned sc_failures)
{ thread->storeCondFailures = sc_failures; }
-#if FULL_SYSTEM
- bool inPalMode() { return cpu->inPalMode(); }
-#endif
-
bool misspeculating() { return false; }
#if !FULL_SYSTEM
@@ -360,16 +361,14 @@ class OzoneCPU : public BaseCPU
bool interval_stats;
- AlphaITB *itb;
- AlphaDTB *dtb;
+ TheISA::ITB *itb;
+ TheISA::DTB *dtb;
System *system;
PhysicalMemory *physmem;
#endif
virtual Port *getPort(const std::string &name, int idx);
- MemObject *mem;
-
FrontEnd *frontEnd;
BackEnd *backEnd;
@@ -583,10 +582,6 @@ class OzoneCPU : public BaseCPU
#if FULL_SYSTEM
Fault hwrei();
- int readIntrFlag() { return thread.intrflag; }
- void setIntrFlag(int val) { thread.intrflag = val; }
- bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
- bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
bool simPalCheck(int palFunc);
void processInterrupts();
#else
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 730158258..39337dbff 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -61,16 +61,14 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
-SimObjectParam<MemObject *> mem;
-
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
@@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
- INIT_PARAM_DFLT(mem, "Memory", NULL),
-
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
@@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
// params->pTable = page_table;
#endif // FULL_SYSTEM
- params->mem = mem;
params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bf547bf94..86c973a0f 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -47,12 +47,12 @@
#if FULL_SYSTEM
#include "arch/faults.hh"
#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/tlb.hh"
-#include "arch/alpha/types.hh"
+#include "arch/tlb.hh"
+#include "arch/types.hh"
+#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "base/callback.hh"
#include "cpu/profile.hh"
-#include "kern/kernel_stats.hh"
#include "mem/physical.hh"
#include "sim/faults.hh"
#include "sim/sim_events.hh"
@@ -93,10 +93,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
#if FULL_SYSTEM
: BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
#else
- : BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem),
+ : BaseCPU(p), thread(this, 0, p->workload[0], 0),
tickEvent(this, p->width),
#endif
- mem(p->mem), comm(5, 5)
+ comm(5, 5)
{
frontEnd = new FrontEnd(p);
backEnd = new BackEnd(p);
@@ -107,7 +107,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
- checker->setMemory(mem);
#if FULL_SYSTEM
checker->setSystem(p->system);
#endif
@@ -198,19 +197,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
-#if !FULL_SYSTEM
- /* Use this port to for syscall emulation writes to memory. */
- Port *mem_port;
- TranslatingPort *trans_port;
- trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
- name(), 0),
- p->workload[0]->pTable,
- false);
- mem_port = p->mem->getPort("functional");
- mem_port->setPeer(trans_port);
- trans_port->setPeer(mem_port);
- thread.setMemPort(trans_port);
-#else
+#if FULL_SYSTEM
Port *mem_port;
FunctionalPort *phys_port;
VirtualPort *virt_port;
@@ -904,7 +891,7 @@ void
OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
{
#if FULL_SYSTEM
- thread->kernelStats = new Kernel::Statistics(cpu->system);
+ thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern");
#endif
}
@@ -1156,37 +1143,31 @@ OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
template <class Impl>
TheISA::MiscReg
-OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
{
- return thread->miscRegFile.readRegWithEffect(misc_reg,
- fault, this);
+ return thread->miscRegFile.readRegWithEffect(misc_reg, this);
}
template <class Impl>
-Fault
+void
OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
- Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val);
+ thread->miscRegFile.setReg(misc_reg, val);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
-
- return ret_fault;
}
template <class Impl>
-Fault
+void
OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
- Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val,
- this);
+ thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
-
- return ret_fault;
}
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index e7390626e..9445a5309 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -230,17 +230,14 @@ class OzoneDynInst : public BaseDynInst<Impl>
// ISA stuff
MiscReg readMiscReg(int misc_reg);
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+ MiscReg readMiscRegWithEffect(int misc_reg);
- Fault setMiscReg(int misc_reg, const MiscReg &val);
+ void setMiscReg(int misc_reg, const MiscReg &val);
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+ void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
Fault hwrei();
- int readIntrFlag();
- void setIntrFlag(int val);
- bool inPalMode();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 9d42ab05b..05a66d77a 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -31,7 +31,10 @@
#include "sim/faults.hh"
#include "config/full_system.hh"
#include "cpu/ozone/dyn_inst.hh"
+
+#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
+#endif
template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
@@ -223,24 +226,24 @@ OzoneDynInst<Impl>::readMiscReg(int misc_reg)
template <class Impl>
TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
{
- return this->thread->readMiscRegWithEffect(misc_reg, fault);
+ return this->thread->readMiscRegWithEffect(misc_reg);
}
template <class Impl>
-Fault
+void
OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
this->setIntResult(val);
- return this->thread->setMiscReg(misc_reg, val);
+ this->thread->setMiscReg(misc_reg, val);
}
template <class Impl>
-Fault
+void
OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- return this->thread->setMiscRegWithEffect(misc_reg, val);
+ this->thread->setMiscRegWithEffect(misc_reg, val);
}
#if FULL_SYSTEM
@@ -249,7 +252,7 @@ template <class Impl>
Fault
OzoneDynInst<Impl>::hwrei()
{
- if (!this->cpu->inPalMode(this->readPC()))
+ if (!(this->readPC() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
@@ -261,27 +264,6 @@ OzoneDynInst<Impl>::hwrei()
}
template <class Impl>
-int
-OzoneDynInst<Impl>::readIntrFlag()
-{
-return this->cpu->readIntrFlag();
-}
-
-template <class Impl>
-void
-OzoneDynInst<Impl>::setIntrFlag(int val)
-{
- this->cpu->setIntrFlag(val);
-}
-
-template <class Impl>
-bool
-OzoneDynInst<Impl>::inPalMode()
-{
- return this->cpu->inPalMode();
-}
-
-template <class Impl>
void
OzoneDynInst<Impl>::trap(Fault fault)
{
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 2bdca35b9..e09e4de9c 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -208,8 +208,6 @@ class FrontEnd
IcachePort icachePort;
- MemObject *mem;
-
RequestPtr memReq;
/** Mask to get a cache block's address. */
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 60c954517..73ca6afbe 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -91,7 +91,6 @@ template <class Impl>
FrontEnd<Impl>::FrontEnd(Params *params)
: branchPred(params),
icachePort(this),
- mem(params->mem),
numInstsReady(params->frontEndLatency, 0),
instBufferSize(0),
maxInstBufferSize(params->maxInstBufferSize),
@@ -463,15 +462,10 @@ Fault
FrontEnd<Impl>::fetchCacheLine()
{
// Read a cache line, based on the current PC.
-#if FULL_SYSTEM
- // Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
-#else
- unsigned flags = 0;
-#endif // FULL_SYSTEM
Fault fault = NoFault;
- if (interruptPending && flags == 0) {
+ //AlphaDep
+ if (interruptPending && (PC & 0x3)) {
return fault;
}
@@ -883,7 +877,11 @@ FrontEnd<Impl>::getInstFromCacheline()
// Get the instruction from the array of the cache line.
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
+#if THE_ISA == ALPHA_ISA
+ ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
+#elif THE_ISA == SPARC_ISA
ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
+#endif
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 8aef9c074..87bf0a7a2 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -152,11 +152,11 @@ InorderBackEnd<Impl>::tick()
#if FULL_SYSTEM
if (interruptBlocked ||
(cpu->checkInterrupts &&
- cpu->check_interrupts() &&
- !cpu->inPalMode())) {
+ cpu->check_interrupts(tc))) {
if (!robEmpty()) {
interruptBlocked = true;
- } else if (robEmpty() && cpu->inPalMode()) {
+ //AlphaDep
+ } else if (robEmpty() && (PC & 0x3)) {
// Will need to let the front end continue a bit until
// we're out of pal mode. Hopefully we never get into an
// infinite loop...
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index c39b9e08b..a181c93f4 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -526,8 +526,7 @@ void
LWBackEnd<Impl>::checkInterrupts()
{
if (cpu->checkInterrupts &&
- cpu->check_interrupts() &&
- !cpu->inPalMode(thread->readPC()) &&
+ cpu->check_interrupts(tc) &&
!trapSquash &&
!tcSquash) {
frontEnd->interruptPending = true;
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index dc58a8285..7e6849668 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -239,8 +239,6 @@ class OzoneLWLSQ {
/** Pointer to the back-end stage. */
BackEnd *be;
- MemObject *mem;
-
class DcachePort : public Port
{
protected:
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 1f3f18502..ee1968626 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -154,8 +154,6 @@ OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
SQIndices.push(i);
}
- mem = params->mem;
-
usedPorts = 0;
cachePorts = params->cachePorts;
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index baaf7c708..e7214d2ba 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 3f63d2e1d..d5ba6a923 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -34,8 +34,11 @@
#include "cpu/ozone/cpu.hh"
//Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace TheISA
+{
+ class DTB;
+ class ITB;
+}
class FUPool;
class MemObject;
class PageTable;
@@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params
public:
#if FULL_SYSTEM
- AlphaITB *itb; AlphaDTB *dtb;
+ TheISA::ITB *itb; TheISA::DTB *dtb;
#else
std::vector<Process *> workload;
#endif // FULL_SYSTEM
@@ -61,8 +64,6 @@ class SimpleParams : public BaseCPU::Params
//Page Table
PageTable *pTable;
- MemObject *mem;
-
//
// Caches
//
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 985e09b52..a71795851 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState {
#if FULL_SYSTEM
OzoneThreadState(CPUType *_cpu, int _thread_num)
- : ThreadState(-1, _thread_num),
+ : ThreadState(_cpu, -1, _thread_num),
intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
{
if (cpu->params->profile) {
@@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState {
}
#else
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
- int _asid, MemObject *mem)
- : ThreadState(-1, _thread_num, _process, _asid, mem),
+ int _asid)
+ : ThreadState(_cpu, -1, _thread_num, _process, _asid),
cpu(_cpu), inSyscall(0), trapPending(0)
{
miscRegFile.clear();
@@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState {
return miscRegFile.readReg(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ MiscReg readMiscRegWithEffect(int misc_reg)
{
- return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+ return miscRegFile.readRegWithEffect(misc_reg, tc);
}
- Fault setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val)
{
- return miscRegFile.setReg(misc_reg, val);
+ miscRegFile.setReg(misc_reg, val);
}
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- return miscRegFile.setRegWithEffect(misc_reg, val, tc);
+ miscRegFile.setRegWithEffect(misc_reg, val, tc);
}
uint64_t readPC()
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 21:47:00 +0000