diff options
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r-- | src/cpu/ozone/checker_builder.cc | 5 | ||||
-rw-r--r-- | src/cpu/ozone/cpu.hh | 5 | ||||
-rw-r--r-- | src/cpu/ozone/cpu_builder.cc | 5 | ||||
-rw-r--r-- | src/cpu/ozone/cpu_impl.hh | 20 | ||||
-rw-r--r-- | src/cpu/ozone/dyn_inst_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/ozone/lw_back_end_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq_impl.hh | 8 | ||||
-rw-r--r-- | src/cpu/ozone/thread_state.hh | 4 |
8 files changed, 26 insertions, 27 deletions
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index 99ba3e308..b4c4686b7 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -65,7 +65,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param<Counter> max_insts_all_threads; Param<Counter> max_loads_any_thread; Param<Counter> max_loads_all_threads; - Param<Counter> stats_reset_inst; Param<Tick> progress_interval; #if FULL_SYSTEM @@ -98,8 +97,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), - INIT_PARAM(stats_reset_inst, - "blah"), INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM @@ -134,7 +131,6 @@ CREATE_SIM_OBJECT(OzoneChecker) params->max_insts_all_threads = 0; params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; - params->stats_reset_inst = 0; params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->warnOnlyOnLoadError = warnOnlyOnLoadError; @@ -149,7 +145,6 @@ CREATE_SIM_OBJECT(OzoneChecker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; - temp = stats_reset_inst; Tick temp2 = progress_interval; temp2++; params->progress_interval = 0; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index ece68282f..8c5be9424 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -33,6 +33,7 @@ #include <set> +#include "arch/regfile.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" @@ -257,8 +258,8 @@ class OzoneCPU : public BaseCPU void setFuncExeInst(Counter new_val) { thread->funcExeInst = new_val; } #endif - void changeRegFileContext(TheISA::RegFile::ContextParam param, - TheISA::RegFile::ContextVal val) + void changeRegFileContext(TheISA::RegContextParam param, + TheISA::RegContextVal val) { panic("Not supported on Alpha!"); } }; diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index e3e4ec433..730158258 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -77,7 +77,6 @@ Param<Counter> max_insts_any_thread; Param<Counter> max_insts_all_threads; Param<Counter> max_loads_any_thread; Param<Counter> max_loads_all_threads; -Param<Counter> stats_reset_inst; Param<Tick> progress_interval; //SimObjectParam<BaseCache *> icache; @@ -210,9 +209,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) "Terminate when all threads have reached this load" "count", 0), - INIT_PARAM_DFLT(stats_reset_inst, - "blah", - 0), INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), // INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), @@ -360,7 +356,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; - params->stats_reset_inst = stats_reset_inst; params->progress_interval = progress_interval; // diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 5c8b5001d..bf547bf94 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -35,6 +35,7 @@ #include "arch/isa_traits.hh" // For MachInst #include "base/trace.hh" #include "cpu/base.hh" +#include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/ozone/cpu.hh" @@ -52,6 +53,7 @@ #include "base/callback.hh" #include "cpu/profile.hh" #include "kern/kernel_stats.hh" +#include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" @@ -102,7 +104,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) _status = Idle; if (p->checker) { - +#if USE_CHECKER BaseCPU *temp_checker = p->checker; checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); checker->setMemory(mem); @@ -240,7 +242,7 @@ template <class Impl> void OzoneCPU<Impl>::switchOut() { - BaseCPU::switchOut(_sampler); + BaseCPU::switchOut(); switchCount = 0; // Front end needs state from back end, so switch out the back end first. backEnd->switchOut(); @@ -468,10 +470,10 @@ OzoneCPU<Impl>::serialize(std::ostream &os) // Use SimpleThread's ability to checkpoint to make it easier to // write out the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; + static SimpleThread temp; nameOut(os, csprintf("%s.xc.0", name())); - temp.copyXC(thread.getXCProxy()); + temp.copyTC(thread.getTC()); temp.serialize(os); } @@ -487,11 +489,11 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) // Use SimpleThread's ability to checkpoint to make it easier to // read in the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; + static SimpleThread temp; - temp.copyXC(thread.getXCProxy()); + temp.copyTC(thread.getTC()); temp.unserialize(cp, csprintf("%s.xc.0", section)); - thread.getXCProxy()->copyArchRegs(temp.getProxy()); + thread.getTC()->copyArchRegs(temp.getTC()); } template <class Impl> @@ -746,11 +748,13 @@ OzoneCPU<Impl>::processInterrupts() if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) { thread.setMiscReg(IPR_ISR, summary); thread.setMiscReg(IPR_INTID, ipl); +#if USE_CHECKER // @todo: Make this more transparent if (checker) { checker->threadBase()->setMiscReg(IPR_ISR, summary); checker->threadBase()->setMiscReg(IPR_INTID, ipl); } +#endif Fault fault = new InterruptFault; fault->invoke(thread.getTC()); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", @@ -872,7 +876,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context) copyArchRegs(old_context); setCpuId(old_context->readCpuId()); - thread->inst = old_context->getInst(); + thread->setInst(old_context->getInst()); #if !FULL_SYSTEM setFuncExeInst(old_context->readFuncExeInst()); #else diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index ba0d70417..db1460eba 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -215,14 +215,14 @@ OzoneDynInst<Impl>::clearMemDependents() } template <class Impl> -MiscReg +TheISA::MiscReg OzoneDynInst<Impl>::readMiscReg(int misc_reg) { return this->thread->readMiscReg(misc_reg); } template <class Impl> -MiscReg +TheISA::MiscReg OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault) { return this->thread->readMiscRegWithEffect(misc_reg, fault); diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index f87a2bc57..c39b9e08b 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -1197,7 +1197,7 @@ LWBackEnd<Impl>::commitInst(int inst_num) // (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; // thread->profilePC = usermode ? 1 : inst->readPC(); thread->profilePC = inst->readPC(); - ProfileNode *node = thread->profile->consume(thread->getXCProxy(), + ProfileNode *node = thread->profile->consume(thread->getTC(), inst->staticInst); if (node) diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 31ffa9d67..4c96ad149 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -121,7 +121,7 @@ OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt) } if (inst->isStore()) { - completeStore(state->idx); + completeStore(inst); } } @@ -178,6 +178,10 @@ OzoneLWLSQ<Impl>::regStats() lsqMemOrderViolation .name(name() + ".memOrderViolation") .desc("Number of memory ordering violations"); +} + +template<class Impl> +void OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr) { cpu = cpu_ptr; @@ -390,7 +394,7 @@ OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst) // Actually probably want the oldest faulting load if (load_fault != NoFault) { DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum); - if (!(inst->req->flags & UNCACHEABLE && !inst->isAtCommit())) { + if (!(inst->req->getFlags() & UNCACHEABLE && !inst->isAtCommit())) { inst->setExecuted(); } // Maybe just set it as can commit here, although that might cause diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index adaa8e71b..c86f3552e 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -68,7 +68,7 @@ struct OzoneThreadState : public ThreadState { #if FULL_SYSTEM OzoneThreadState(CPUType *_cpu, int _thread_num) : ThreadState(-1, _thread_num), - cpu(_cpu), intrflag(0), inSyscall(0), trapPending(0) + intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { profile = new FunctionProfile(cpu->params->system->kernelSymtab); @@ -151,7 +151,7 @@ struct OzoneThreadState : public ThreadState { void dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); - profile->dump(xcProxy, *os); + profile->dump(tc, *os); } #endif }; |