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-rw-r--r--src/cpu/ozone/back_end.hh92
-rw-r--r--src/cpu/ozone/cpu.hh4
-rw-r--r--src/cpu/ozone/front_end.hh40
-rw-r--r--src/cpu/ozone/inorder_back_end.hh2
-rw-r--r--src/cpu/ozone/inst_queue.hh32
-rw-r--r--src/cpu/ozone/lsq_unit.hh2
-rw-r--r--src/cpu/ozone/lw_back_end.hh84
-rw-r--r--src/cpu/ozone/lw_lsq.hh4
8 files changed, 130 insertions, 130 deletions
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 84429f3c1..ca858ce2e 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -157,13 +157,13 @@ class BackEnd
int numInsts;
int width;
- Stats::VectorDistribution<> occ_dist;
+ Stats::VectorDistribution occ_dist;
- Stats::Vector<> inst_count;
- Stats::Vector<> peak_inst_count;
- Stats::Scalar<> empty_count;
- Stats::Scalar<> current_count;
- Stats::Scalar<> fullCount;
+ Stats::Vector inst_count;
+ Stats::Vector peak_inst_count;
+ Stats::Scalar empty_count;
+ Stats::Scalar current_count;
+ Stats::Scalar fullCount;
Stats::Formula occ_rate;
Stats::Formula avg_residency;
@@ -371,45 +371,45 @@ class BackEnd
bool fetchRedirect[Impl::MaxThreads];
// number of cycles stalled for D-cache misses
-/* Stats::Scalar<> dcacheStallCycles;
+/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
- Stats::Vector<> rob_cap_events;
- Stats::Vector<> rob_cap_inst_count;
- Stats::Vector<> iq_cap_events;
- Stats::Vector<> iq_cap_inst_count;
+ Stats::Vector rob_cap_events;
+ Stats::Vector rob_cap_inst_count;
+ Stats::Vector iq_cap_events;
+ Stats::Vector iq_cap_inst_count;
// total number of instructions executed
- Stats::Vector<> exe_inst;
- Stats::Vector<> exe_swp;
- Stats::Vector<> exe_nop;
- Stats::Vector<> exe_refs;
- Stats::Vector<> exe_loads;
- Stats::Vector<> exe_branches;
+ Stats::Vector exe_inst;
+ Stats::Vector exe_swp;
+ Stats::Vector exe_nop;
+ Stats::Vector exe_refs;
+ Stats::Vector exe_loads;
+ Stats::Vector exe_branches;
- Stats::Vector<> issued_ops;
+ Stats::Vector issued_ops;
// total number of loads forwaded from LSQ stores
- Stats::Vector<> lsq_forw_loads;
+ Stats::Vector lsq_forw_loads;
// total number of loads ignored due to invalid addresses
- Stats::Vector<> inv_addr_loads;
+ Stats::Vector inv_addr_loads;
// total number of software prefetches ignored due to invalid addresses
- Stats::Vector<> inv_addr_swpfs;
+ Stats::Vector inv_addr_swpfs;
// ready loads blocked due to memory disambiguation
- Stats::Vector<> lsq_blocked_loads;
+ Stats::Vector lsq_blocked_loads;
- Stats::Scalar<> lsqInversion;
+ Stats::Scalar lsqInversion;
- Stats::Vector<> n_issued_dist;
- Stats::VectorDistribution<> issue_delay_dist;
+ Stats::Vector n_issued_dist;
+ Stats::VectorDistribution issue_delay_dist;
- Stats::VectorDistribution<> queue_res_dist;
+ Stats::VectorDistribution queue_res_dist;
/*
- Stats::Vector<> stat_fu_busy;
- Stats::Vector2d<> stat_fuBusy;
- Stats::Vector<> dist_unissued;
- Stats::Vector2d<> stat_issued_inst_type;
+ Stats::Vector stat_fu_busy;
+ Stats::Vector2d stat_fuBusy;
+ Stats::Vector dist_unissued;
+ Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -422,34 +422,34 @@ class BackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
- Stats::Vector<> writeback_count;
- Stats::Vector<> producer_inst;
- Stats::Vector<> consumer_inst;
- Stats::Vector<> wb_penalized;
+ Stats::Vector writeback_count;
+ Stats::Vector producer_inst;
+ Stats::Vector consumer_inst;
+ Stats::Vector wb_penalized;
Stats::Formula wb_rate;
Stats::Formula wb_fanout;
Stats::Formula wb_penalized_rate;
// total number of instructions committed
- Stats::Vector<> stat_com_inst;
- Stats::Vector<> stat_com_swp;
- Stats::Vector<> stat_com_refs;
- Stats::Vector<> stat_com_loads;
- Stats::Vector<> stat_com_membars;
- Stats::Vector<> stat_com_branches;
+ Stats::Vector stat_com_inst;
+ Stats::Vector stat_com_swp;
+ Stats::Vector stat_com_refs;
+ Stats::Vector stat_com_loads;
+ Stats::Vector stat_com_membars;
+ Stats::Vector stat_com_branches;
- Stats::Distribution<> n_committed_dist;
+ Stats::Distribution n_committed_dist;
- Stats::Scalar<> commit_eligible_samples;
- Stats::Vector<> commit_eligible;
+ Stats::Scalar commit_eligible_samples;
+ Stats::Vector commit_eligible;
- Stats::Scalar<> ROB_fcount;
+ Stats::Scalar ROB_fcount;
Stats::Formula ROB_full_rate;
- Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Vector ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
- Stats::VectorDistribution<> ROB_occ_dist;
+ Stats::VectorDistribution ROB_occ_dist;
public:
void dumpInsts();
};
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 054fc1aa1..0bfb4bfa9 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -390,7 +390,7 @@ class OzoneCPU : public BaseCPU
Counter startNumLoad;
// number of idle cycles
- Stats::Average<> notIdleFraction;
+ Stats::Average notIdleFraction;
Stats::Formula idleFraction;
public:
@@ -473,7 +473,7 @@ class OzoneCPU : public BaseCPU
bool lockFlag;
- Stats::Scalar<> quiesceCycles;
+ Stats::Scalar quiesceCycles;
Checker<DynInstPtr> *checker;
};
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index fac243449..38fc89e3f 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -275,48 +275,48 @@ class FrontEnd
private:
// number of idle cycles
/*
- Stats::Average<> notIdleFraction;
+ Stats::Average notIdleFraction;
Stats::Formula idleFraction;
*/
// @todo: Consider making these vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */
- Stats::Scalar<> icacheStallCycles;
+ Stats::Scalar icacheStallCycles;
/** Stat for total number of fetched instructions. */
- Stats::Scalar<> fetchedInsts;
- Stats::Scalar<> fetchedBranches;
+ Stats::Scalar fetchedInsts;
+ Stats::Scalar fetchedBranches;
/** Stat for total number of predicted branches. */
- Stats::Scalar<> predictedBranches;
+ Stats::Scalar predictedBranches;
/** Stat for total number of cycles spent fetching. */
- Stats::Scalar<> fetchCycles;
+ Stats::Scalar fetchCycles;
- Stats::Scalar<> fetchIdleCycles;
+ Stats::Scalar fetchIdleCycles;
/** Stat for total number of cycles spent squashing. */
- Stats::Scalar<> fetchSquashCycles;
+ Stats::Scalar fetchSquashCycles;
/** Stat for total number of cycles spent blocked due to other stages in
* the pipeline.
*/
- Stats::Scalar<> fetchBlockedCycles;
+ Stats::Scalar fetchBlockedCycles;
/** Stat for total number of fetched cache lines. */
- Stats::Scalar<> fetchedCacheLines;
+ Stats::Scalar fetchedCacheLines;
- Stats::Scalar<> fetchIcacheSquashes;
+ Stats::Scalar fetchIcacheSquashes;
/** Distribution of number of instructions fetched each cycle. */
- Stats::Distribution<> fetchNisnDist;
-// Stats::Vector<> qfull_iq_occupancy;
-// Stats::VectorDistribution<> qfull_iq_occ_dist_;
+ Stats::Distribution fetchNisnDist;
+// Stats::Vector qfull_iq_occupancy;
+// Stats::VectorDistribution qfull_iq_occ_dist_;
Stats::Formula idleRate;
Stats::Formula branchRate;
Stats::Formula fetchRate;
- Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
+ Stats::Scalar IFQCount; // cumulative IFQ occupancy
Stats::Formula IFQOccupancy;
Stats::Formula IFQLatency;
- Stats::Scalar<> IFQFcount; // cumulative IFQ full count
+ Stats::Scalar IFQFcount; // cumulative IFQ full count
Stats::Formula IFQFullRate;
- Stats::Scalar<> dispatchCountStat;
- Stats::Scalar<> dispatchedSerializing;
- Stats::Scalar<> dispatchedTempSerializing;
- Stats::Scalar<> dispatchSerializeStallCycles;
+ Stats::Scalar dispatchCountStat;
+ Stats::Scalar dispatchedSerializing;
+ Stats::Scalar dispatchedTempSerializing;
+ Stats::Scalar dispatchSerializeStallCycles;
Stats::Formula dispatchRate;
Stats::Formula regIntFull;
Stats::Formula regFpFull;
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 0840591e0..e930144be 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -192,7 +192,7 @@ class InorderBackEnd
TimeBuffer<CommStruct> *comm;
// number of cycles stalled for D-cache misses
- Stats::Scalar<> dcacheStallCycles;
+ Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
};
diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh
index a11d5204b..e840d5c21 100644
--- a/src/cpu/ozone/inst_queue.hh
+++ b/src/cpu/ozone/inst_queue.hh
@@ -473,35 +473,35 @@ class InstQueue
void dumpInsts();
/** Stat for number of instructions added. */
- Stats::Scalar<> iqInstsAdded;
+ Stats::Scalar iqInstsAdded;
/** Stat for number of non-speculative instructions added. */
- Stats::Scalar<> iqNonSpecInstsAdded;
-// Stats::Scalar<> iqIntInstsAdded;
+ Stats::Scalar iqNonSpecInstsAdded;
+// Stats::Scalar iqIntInstsAdded;
/** Stat for number of integer instructions issued. */
- Stats::Scalar<> iqIntInstsIssued;
-// Stats::Scalar<> iqFloatInstsAdded;
+ Stats::Scalar iqIntInstsIssued;
+// Stats::Scalar iqFloatInstsAdded;
/** Stat for number of floating point instructions issued. */
- Stats::Scalar<> iqFloatInstsIssued;
-// Stats::Scalar<> iqBranchInstsAdded;
+ Stats::Scalar iqFloatInstsIssued;
+// Stats::Scalar iqBranchInstsAdded;
/** Stat for number of branch instructions issued. */
- Stats::Scalar<> iqBranchInstsIssued;
-// Stats::Scalar<> iqMemInstsAdded;
+ Stats::Scalar iqBranchInstsIssued;
+// Stats::Scalar iqMemInstsAdded;
/** Stat for number of memory instructions issued. */
- Stats::Scalar<> iqMemInstsIssued;
-// Stats::Scalar<> iqMiscInstsAdded;
+ Stats::Scalar iqMemInstsIssued;
+// Stats::Scalar iqMiscInstsAdded;
/** Stat for number of miscellaneous instructions issued. */
- Stats::Scalar<> iqMiscInstsIssued;
+ Stats::Scalar iqMiscInstsIssued;
/** Stat for number of squashed instructions that were ready to issue. */
- Stats::Scalar<> iqSquashedInstsIssued;
+ Stats::Scalar iqSquashedInstsIssued;
/** Stat for number of squashed instructions examined when squashing. */
- Stats::Scalar<> iqSquashedInstsExamined;
+ Stats::Scalar iqSquashedInstsExamined;
/** Stat for number of squashed instruction operands examined when
* squashing.
*/
- Stats::Scalar<> iqSquashedOperandsExamined;
+ Stats::Scalar iqSquashedOperandsExamined;
/** Stat for number of non-speculative instructions removed due to a squash.
*/
- Stats::Scalar<> iqSquashedNonSpecRemoved;
+ Stats::Scalar iqSquashedNonSpecRemoved;
};
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 981682c26..47be245e5 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -331,7 +331,7 @@ class OzoneLSQ {
//list<InstSeqNum> mshrSeqNums;
- //Stats::Scalar<> dcacheStallCycles;
+ //Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
/** Wire to read information from the issue stage time queue. */
diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index 8ab50d5c9..4a1657c9b 100644
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -326,47 +326,47 @@ class LWBackEnd
bool exactFullStall;
// number of cycles stalled for D-cache misses
-/* Stats::Scalar<> dcacheStallCycles;
+/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
- Stats::Vector<> robCapEvents;
- Stats::Vector<> robCapInstCount;
- Stats::Vector<> iqCapEvents;
- Stats::Vector<> iqCapInstCount;
+ Stats::Vector robCapEvents;
+ Stats::Vector robCapInstCount;
+ Stats::Vector iqCapEvents;
+ Stats::Vector iqCapInstCount;
// total number of instructions executed
- Stats::Vector<> exeInst;
- Stats::Vector<> exeSwp;
- Stats::Vector<> exeNop;
- Stats::Vector<> exeRefs;
- Stats::Vector<> exeLoads;
- Stats::Vector<> exeBranches;
+ Stats::Vector exeInst;
+ Stats::Vector exeSwp;
+ Stats::Vector exeNop;
+ Stats::Vector exeRefs;
+ Stats::Vector exeLoads;
+ Stats::Vector exeBranches;
- Stats::Vector<> issuedOps;
+ Stats::Vector issuedOps;
// total number of loads forwaded from LSQ stores
- Stats::Vector<> lsqForwLoads;
+ Stats::Vector lsqForwLoads;
// total number of loads ignored due to invalid addresses
- Stats::Vector<> invAddrLoads;
+ Stats::Vector invAddrLoads;
// total number of software prefetches ignored due to invalid addresses
- Stats::Vector<> invAddrSwpfs;
+ Stats::Vector invAddrSwpfs;
// ready loads blocked due to memory disambiguation
- Stats::Vector<> lsqBlockedLoads;
+ Stats::Vector lsqBlockedLoads;
- Stats::Scalar<> lsqInversion;
+ Stats::Scalar lsqInversion;
- Stats::Vector<> nIssuedDist;
+ Stats::Vector nIssuedDist;
/*
- Stats::VectorDistribution<> issueDelayDist;
+ Stats::VectorDistribution issueDelayDist;
- Stats::VectorDistribution<> queueResDist;
+ Stats::VectorDistribution queueResDist;
*/
/*
- Stats::Vector<> stat_fu_busy;
- Stats::Vector2d<> stat_fuBusy;
- Stats::Vector<> dist_unissued;
- Stats::Vector2d<> stat_issued_inst_type;
+ Stats::Vector stat_fu_busy;
+ Stats::Vector2d stat_fuBusy;
+ Stats::Vector dist_unissued;
+ Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -379,37 +379,37 @@ class LWBackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
- Stats::Vector<> writebackCount;
- Stats::Vector<> producerInst;
- Stats::Vector<> consumerInst;
- Stats::Vector<> wbPenalized;
+ Stats::Vector writebackCount;
+ Stats::Vector producerInst;
+ Stats::Vector consumerInst;
+ Stats::Vector wbPenalized;
Stats::Formula wbRate;
Stats::Formula wbFanout;
Stats::Formula wbPenalizedRate;
// total number of instructions committed
- Stats::Vector<> statComInst;
- Stats::Vector<> statComSwp;
- Stats::Vector<> statComRefs;
- Stats::Vector<> statComLoads;
- Stats::Vector<> statComMembars;
- Stats::Vector<> statComBranches;
+ Stats::Vector statComInst;
+ Stats::Vector statComSwp;
+ Stats::Vector statComRefs;
+ Stats::Vector statComLoads;
+ Stats::Vector statComMembars;
+ Stats::Vector statComBranches;
- Stats::Distribution<> nCommittedDist;
+ Stats::Distribution nCommittedDist;
- Stats::Scalar<> commitEligibleSamples;
- Stats::Vector<> commitEligible;
+ Stats::Scalar commitEligibleSamples;
+ Stats::Vector commitEligible;
- Stats::Vector<> squashedInsts;
- Stats::Vector<> ROBSquashedInsts;
+ Stats::Vector squashedInsts;
+ Stats::Vector ROBSquashedInsts;
- Stats::Scalar<> ROBFcount;
+ Stats::Scalar ROBFcount;
Stats::Formula ROBFullRate;
- Stats::Vector<> ROBCount; // cumulative ROB occupancy
+ Stats::Vector ROBCount; // cumulative ROB occupancy
Stats::Formula ROBOccRate;
-// Stats::VectorDistribution<> ROBOccDist;
+// Stats::VectorDistribution ROBOccDist;
public:
void dumpInsts();
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 2525da76e..4f8101bc0 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -411,9 +411,9 @@ class OzoneLWLSQ {
//list<InstSeqNum> mshrSeqNums;
/** Tota number of memory ordering violations. */
- Stats::Scalar<> lsqMemOrderViolation;
+ Stats::Scalar lsqMemOrderViolation;
- //Stats::Scalar<> dcacheStallCycles;
+ //Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// Make these per thread?
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 05:42:43 +0000