diff options
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r-- | src/cpu/ozone/OzoneCPU.py | 3 | ||||
-rw-r--r-- | src/cpu/ozone/cpu.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/cpu_impl.hh | 12 | ||||
-rw-r--r-- | src/cpu/ozone/front_end.hh | 5 | ||||
-rw-r--r-- | src/cpu/ozone/front_end_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq.hh | 7 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq_impl.hh | 6 |
7 files changed, 3 insertions, 38 deletions
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py index d50d8d715..b4f37220c 100644 --- a/src/cpu/ozone/OzoneCPU.py +++ b/src/cpu/ozone/OzoneCPU.py @@ -36,9 +36,6 @@ class DerivOzoneCPU(BaseCPU): numThreads = Param.Unsigned("number of HW thread contexts") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") frontEndLatency = Param.Unsigned("Front end latency") diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index d2b90bff3..1bd2ee25b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -316,8 +316,6 @@ class OzoneCPU : public BaseCPU System *system; PhysicalMemory *physmem; - virtual Port *getPort(const std::string &name, int idx); - FrontEnd *frontEnd; BackEnd *backEnd; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index b111d4425..3a32c07c6 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -391,18 +391,6 @@ OzoneCPU<Impl>::init() } template <class Impl> -Port * -OzoneCPU<Impl>::getPort(const std::string &if_name, int idx) -{ - if (if_name == "dcache_port") - return backEnd->getDcachePort(); - else if (if_name == "icache_port") - return frontEnd->getIcachePort(); - else - panic("No Such Port\n"); -} - -template <class Impl> void OzoneCPU<Impl>::serialize(std::ostream &os) { diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index 41b86aab8..6c63bf8d9 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -68,7 +68,7 @@ class FrontEnd /** IcachePort class. Handles doing the communication with the * cache/memory. */ - class IcachePort : public Port + class IcachePort : public MasterPort { protected: /** Pointer to FE. */ @@ -87,9 +87,6 @@ class FrontEnd /** Functional version of receive. Panics. */ virtual void recvFunctional(PacketPtr pkt); - /** Receives range change. */ - virtual void recvRangeChange(); - /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ virtual bool recvTiming(PacketPtr pkt); diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 2c9c70872..12aa0a321 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -59,12 +59,6 @@ FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt) } template<class Impl> -void -FrontEnd<Impl>::IcachePort::recvRangeChange() -{ -} - -template<class Impl> bool FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt) { diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index 809725c0d..a581b242f 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -240,7 +240,7 @@ class OzoneLWLSQ { /** Pointer to the back-end stage. */ BackEnd *be; - class DcachePort : public Port + class DcachePort : public MasterPort { protected: OzoneLWLSQ *lsq; @@ -255,13 +255,10 @@ class OzoneLWLSQ { virtual void recvFunctional(PacketPtr pkt); - virtual void recvRangeChange(); - /** * Is a snooper due to LSQ maintenance */ - virtual bool isSnooping() - { return true; } + virtual bool isSnooping() const { return true; } virtual bool recvTiming(PacketPtr pkt); diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 82d0b4e8b..c0c6d7276 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -75,12 +75,6 @@ OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt) } template <class Impl> -void -OzoneLWLSQ<Impl>::DcachePort::recvRangeChange() -{ -} - -template <class Impl> bool OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) { |