diff options
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r-- | src/cpu/ozone/back_end.hh | 8 | ||||
-rw-r--r-- | src/cpu/ozone/cpu.hh | 4 | ||||
-rw-r--r-- | src/cpu/ozone/cpu_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/ozone/front_end_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/inorder_back_end.hh | 18 | ||||
-rw-r--r-- | src/cpu/ozone/inst_queue_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/lsq_unit.hh | 8 | ||||
-rw-r--r-- | src/cpu/ozone/lsq_unit_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/lw_back_end_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq_impl.hh | 4 |
11 files changed, 33 insertions, 33 deletions
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh index 7a2da3239..95e079d0d 100644 --- a/src/cpu/ozone/back_end.hh +++ b/src/cpu/ozone/back_end.hh @@ -468,7 +468,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx) if (fault == NoFault && dcacheInterface) { memReq->cmd = Read; memReq->completionEvent = NULL; - memReq->time = curTick; + memReq->time = curTick(); memReq->flags &= ~INST_READ; MemAccessResult result = dcacheInterface->access(memReq); @@ -481,7 +481,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx) --funcExeInst; memReq->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); // status = DcacheMissStall; DPRINTF(OzoneCPU, "Dcache miss stall!\n"); @@ -510,7 +510,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx) memReq->cmd = Write; memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; - memReq->time = curTick; + memReq->time = curTick(); memReq->flags &= ~INST_READ; MemAccessResult result = dcacheInterface->access(memReq); @@ -519,7 +519,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx) // at some point. if (result != MA_HIT && dcacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); // status = DcacheMissStall; DPRINTF(OzoneCPU, "Dcache miss stall!\n"); diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index fcc5602eb..1b196feb4 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -277,9 +277,9 @@ class OzoneCPU : public BaseCPU void scheduleTickEvent(int delay) { if (tickEvent.squashed()) - tickEvent.reschedule(curTick + ticks(delay)); + tickEvent.reschedule(curTick() + ticks(delay)); else if (!tickEvent.scheduled()) - tickEvent.schedule(curTick + ticks(delay)); + tickEvent.schedule(curTick() + ticks(delay)); } /// Unschedule tick event, regardless of its current state. diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index a22ada5d0..dd6c3dcf1 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -301,7 +301,7 @@ OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU) if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; - tickEvent.schedule(curTick); + tickEvent.schedule(curTick()); } } // Nothing running, change status to reflect that we're no longer @@ -525,7 +525,7 @@ OzoneCPU<Impl>::tick() comInstEventQueue[0]->serviceEvents(numInst); if (!tickEvent.scheduled() && _status == Running) - tickEvent.schedule(curTick + ticks(1)); + tickEvent.schedule(curTick() + ticks(1)); } template <class Impl> diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 884136927..d7ed0b77a 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -52,7 +52,7 @@ Tick FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt) { panic("FrontEnd doesn't expect recvAtomic callback!"); - return curTick; + return curTick(); } template<class Impl> @@ -432,7 +432,7 @@ FrontEnd<Impl>::tick() #if FULL_SYSTEM if (inst->isQuiesce()) { -// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick); +// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick()); status = QuiescePending; break; } @@ -894,7 +894,7 @@ FrontEnd<Impl>::getInstFromCacheline() instruction->staticInst->disassemble(PC)); instruction->traceData = - Trace::getInstRecord(curTick, tc, + Trace::getInstRecord(curTick(), tc, instruction->staticInst, instruction->readPC()); diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 9c2699610..fcdc2a38a 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -210,7 +210,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) if (fault == NoFault && dcacheInterface) { memReq->cmd = Read; memReq->completionEvent = NULL; - memReq->time = curTick; + memReq->time = curTick(); MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -220,7 +220,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) // Fix this hack for keeping funcExeInst correct with loads that // are executed twice. memReq->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); status = DcacheMissLoadStall; DPRINTF(IBE, "Dcache miss stall!\n"); @@ -246,7 +246,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->cmd = Write; // memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; - memReq->time = curTick; + memReq->time = curTick(); MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -254,7 +254,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) // at some point. if (result != MA_HIT) { memReq->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); status = DcacheMissStoreStall; DPRINTF(IBE, "Dcache miss stall!\n"); @@ -280,7 +280,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx) // Fault fault = cpu->translateDataReadReq(req); req->cmd = Read; req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); assert(!req->data); req->data = new uint8_t[64]; Fault fault = cpu->read(req, data); @@ -295,7 +295,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx) // at some point. if (result != MA_HIT) { req->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); status = DcacheMissLoadStall; DPRINTF(IBE, "Dcache miss load stall!\n"); @@ -320,7 +320,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) req->cmd = Write; req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); assert(!req->data); req->data = new uint8_t[64]; memcpy(req->data, (uint8_t *)&data, req->size); @@ -347,7 +347,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) req->data = new uint8_t[64]; memcpy(req->data,(uint8_t *)&data,req->size); req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); MemAccessResult result = dcacheInterface->access(req); // Ugly hack to get an event scheduled *only* if the access is @@ -355,7 +355,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) // at some point. if (result != MA_HIT) { req->completionEvent = &cacheCompletionEvent; - lastDcacheStall = curTick; + lastDcacheStall = curTick(); // unscheduleTickEvent(); status = DcacheMissStoreStall; DPRINTF(IBE, "Dcache miss store stall!\n"); diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh index ae2e3b09b..0068f2977 100644 --- a/src/cpu/ozone/inst_queue_impl.hh +++ b/src/cpu/ozone/inst_queue_impl.hh @@ -673,7 +673,7 @@ InstQueue<Impl>::scheduleReadyInsts() FUCompletion *execution = new FUCompletion(issuing_inst, idx, this); - execution->schedule(curTick + issue_latency - 1); + execution->schedule(curTick() + issue_latency - 1); } else { i2e_info->insts[exec_queue_slot++] = issuing_inst; i2e_info->size++; diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh index d8e402b65..0216c5013 100644 --- a/src/cpu/ozone/lsq_unit.hh +++ b/src/cpu/ozone/lsq_unit.hh @@ -485,7 +485,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx) req->cmd = Read; assert(!req->completionEvent); req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); assert(!req->data); req->data = new uint8_t[64]; @@ -502,7 +502,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx) // We'll say this has a 1 cycle load-store forwarding latency // for now. // FIXME - Need to make this a parameter. - wb->schedule(curTick); + wb->schedule(curTick()); // Should keep track of stat for forwarded data return NoFault; @@ -562,7 +562,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx) // Setup MemReq pointer req->cmd = Read; req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); assert(!req->data); req->data = new uint8_t[64]; @@ -585,7 +585,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx) DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n", inst->seqNum); - lastDcacheStall = curTick; + lastDcacheStall = curTick(); _status = DcacheMissStall; diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index dd44adf6e..f36b870d8 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -557,7 +557,7 @@ OzoneLSQ<Impl>::writebackStores() // Fault fault = cpu->translateDataReadReq(req); req->cmd = Write; req->completionEvent = NULL; - req->time = curTick; + req->time = curTick(); assert(!req->data); req->data = new uint8_t[64]; memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size); @@ -615,7 +615,7 @@ OzoneLSQ<Impl>::writebackStores() req->completionEvent = new StoreCompletionEvent(storeWBIdx, wb, this); - lastDcacheStall = curTick; + lastDcacheStall = curTick(); _status = DcacheMissStall; @@ -637,7 +637,7 @@ OzoneLSQ<Impl>::writebackStores() typename BackEnd::LdWritebackEvent *wb = new typename BackEnd::LdWritebackEvent(storeQueue[storeWBIdx].inst, be); - wb->schedule(curTick); + wb->schedule(curTick()); } completeStore(storeWBIdx); diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index 465fccbdb..8000c142e 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency) TrapEvent *trap = new TrapEvent(this); - trap->schedule(curTick + cpu->ticks(latency)); + trap->schedule(curTick() + cpu->ticks(latency)); thread->trapPending = true; } @@ -1226,7 +1226,7 @@ LWBackEnd<Impl>::commitInst(int inst_num) // Write the done sequence number here. toIEW->doneSeqNum = inst->seqNum; - lastCommitCycle = curTick; + lastCommitCycle = curTick(); #if FULL_SYSTEM int count = 0; diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index ee0312969..9605f175e 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -581,7 +581,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx) // We'll say this has a 1 cycle load-store forwarding latency // for now. // @todo: Need to make this a parameter. - wb->schedule(curTick); + wb->schedule(curTick()); // Should keep track of stat for forwarded data return NoFault; diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index c714c5d38..0c4e4b9c7 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -65,7 +65,7 @@ Tick OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt) { panic("O3CPU model does not work with atomic mode!"); - return curTick; + return curTick(); } template <class Impl> @@ -677,7 +677,7 @@ OzoneLWLSQ<Impl>::writebackStores() be->addDcacheMiss(inst); - lastDcacheStall = curTick; + lastDcacheStall = curTick(); _status = DcacheMissStall; |