4 files changed, 5 insertions, 9 deletions

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 845cbbd95..491e6ba93 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -332,7 +332,7 @@ class OzoneCPU : public BaseCPU
     Status _status;
 
   public:
-    void post_interrupt(int int_num, int index);
+    void postInterrupt(int int_num, int index);
 
     void zero_fill_64(Addr addr) {
         static int warned = 0;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index c8e0dfe3d..a7efa3596 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -579,9 +579,9 @@ OzoneCPU<Impl>::dbg_vtophys(Addr addr)
 #if FULL_SYSTEM
 template <class Impl>
 void
-OzoneCPU<Impl>::post_interrupt(int int_num, int index)
+OzoneCPU<Impl>::postInterrupt(int int_num, int index)
 {
-    BaseCPU::post_interrupt(int_num, index);
+    BaseCPU::postInterrupt(int_num, index);
 
     if (_status == Idle) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index cf8634a42..798b628d6 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -149,8 +149,7 @@ InorderBackEnd<Impl>::tick()
     // if (interrupt) then set thread PC, stall front end, record that
     // I'm waiting for it to drain.  (for now just squash)
 #if FULL_SYSTEM
-    if (interruptBlocked ||
-        cpu->check_interrupts(tc)) {
+    if (interruptBlocked || cpu->checkInterrupts(tc)) {
         if (!robEmpty()) {
             interruptBlocked = true;
         //AlphaDep
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index a5d79a789..60c42edd3 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -525,10 +525,7 @@ template <class Impl>
 void
 LWBackEnd<Impl>::checkInterrupts()
 {
-    if (cpu->checkInterrupts &&
-        cpu->check_interrupts(tc) &&
-        !trapSquash &&
-        !tcSquash) {
+    if (cpu->checkInterrupts(tc) && !trapSquash && !tcSquash) {
         frontEnd->interruptPending = true;
         if (robEmpty() && !LSQ.hasStoresToWB()) {
             // Will need to squash all instructions currently in flight and have