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-rw-r--r--src/cpu/ozone/cpu.hh4
-rw-r--r--src/cpu/ozone/thread_state.hh2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 2b2ed7b3e..c1373944d 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -361,8 +361,8 @@ class OzoneCPU : public BaseCPU
bool interval_stats;
- AlphaITB *itb;
- AlphaDTB *dtb;
+ TheISA::ITB *itb;
+ TheISA::DTB *dtb;
System *system;
PhysicalMemory *physmem;
#endif
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c4d16b3af..a71795851 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState {
MiscReg readMiscRegWithEffect(int misc_reg)
{
- return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+ return miscRegFile.readRegWithEffect(misc_reg, tc);
}
void setMiscReg(int misc_reg, const MiscReg &val)