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-rw-r--r--src/cpu/ozone/OzoneCPU.py11
-rw-r--r--src/cpu/ozone/SConscript5
-rw-r--r--src/cpu/ozone/cpu_impl.hh13
-rw-r--r--src/cpu/ozone/front_end_impl.hh8
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh10
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh7
6 files changed, 11 insertions, 43 deletions
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index 2c7b8475f..d50d8d715 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -29,18 +29,13 @@
from m5.defines import buildEnv
from m5.params import *
from BaseCPU import BaseCPU
-
-if buildEnv['USE_CHECKER']:
- from OzoneChecker import OzoneChecker
+from OzoneChecker import OzoneChecker
class DerivOzoneCPU(BaseCPU):
type = 'DerivOzoneCPU'
numThreads = Param.Unsigned("number of HW thread contexts")
- if buildEnv['USE_CHECKER']:
- checker = Param.BaseCPU("Checker CPU")
-
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
@@ -123,3 +118,7 @@ class DerivOzoneCPU(BaseCPU):
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+ # If the CheckerCPU is brought back to useability in the OzoneCPU, create a
+ # function here called addCheckerCpu() to create a non-NULL Checker and
+ # connect its TLBs (if needed)
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index d26410ac2..6c966eb66 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -53,6 +53,5 @@ if 'OzoneCPU' in env['CPU_MODELS']:
CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
- if env['USE_CHECKER']:
- SimObject('OzoneChecker.py')
- Source('checker_builder.cc')
+ SimObject('OzoneChecker.py')
+ Source('checker_builder.cc')
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 65545b6aa..b111d4425 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -38,7 +38,7 @@
#include "base/callback.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/thread_context.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
@@ -56,10 +56,6 @@
#include "sim/stats.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/thread_context.hh"
-#endif
-
using namespace TheISA;
template <class Impl>
@@ -97,16 +93,12 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
_status = Idle;
if (p->checker) {
-#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setSystem(p->system);
checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
thread.tc = checkerTC;
tc = checkerTC;
-#else
- panic("Checker enabled but not compiled in!");
-#endif
} else {
// If checker is not being used, then the xcProxy points
// directly to the CPU's ExecContext.
@@ -215,10 +207,9 @@ OzoneCPU<Impl>::signalSwitched()
if (++switchCount == 2) {
backEnd->doSwitchOut();
frontEnd->doSwitchOut();
-#if USE_CHECKER
+
if (checker)
checker->switchOut();
-#endif
_status = SwitchedOut;
#ifndef NDEBUG
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index e7255d75f..2c9c70872 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -32,7 +32,7 @@
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/exetrace.hh"
#include "cpu/thread_context.hh"
@@ -41,10 +41,6 @@
#include "mem/request.hh"
#include "sim/faults.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
using namespace TheISA;
template<class Impl>
@@ -137,11 +133,9 @@ FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
icachePort.setName(this->name() + "-iport");
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setIcachePort(&icachePort);
}
-#endif
}
template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index c06a58754..1570c86ee 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -29,14 +29,10 @@
*/
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/ozone/lw_back_end.hh"
#include "cpu/op_class.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
template <class Impl>
void
LWBackEnd<Impl>::generateTrapEvent(Tick latency)
@@ -1133,11 +1129,9 @@ LWBackEnd<Impl>::commitInst(int inst_num)
// Use checker prior to updating anything due to traps or PC
// based events.
-#if USE_CHECKER
if (checker) {
checker->verify(inst);
}
-#endif
if (inst_fault != NoFault) {
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
@@ -1153,11 +1147,9 @@ LWBackEnd<Impl>::commitInst(int inst_num)
DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
return false;
}
-#if USE_CHECKER
else if (checker && inst->isStore()) {
checker->verify(inst);
}
-#endif
handleFault(inst_fault);
return false;
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index d80cdcf8c..82d0b4e8b 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -30,7 +30,6 @@
#include "base/str.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "sim/fault_fwd.hh"
@@ -181,11 +180,9 @@ OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
cpu = cpu_ptr;
dcachePort.setName(this->name() + "-dport");
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setDcachePort(&dcachePort);
}
-#endif
}
template<class Impl>
@@ -846,11 +843,9 @@ OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
// only works so long as the checker doesn't try to
// verify the value in memory for stores.
inst->setCompleted();
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->verify(inst);
}
-#endif
}
}
@@ -914,11 +909,9 @@ OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
--stores;
inst->setCompleted();
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->verify(inst);
}
-#endif
}
template <class Impl>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 02:11:56 +0000