diff options
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r-- | src/cpu/ozone/back_end_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/inorder_back_end.hh | 2 | ||||
-rw-r--r-- | src/cpu/ozone/lsq_unit_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq.hh | 4 | ||||
-rw-r--r-- | src/cpu/ozone/lw_lsq_impl.hh | 8 |
5 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh index ef3b0f182..7753a83b5 100644 --- a/src/cpu/ozone/back_end_impl.hh +++ b/src/cpu/ozone/back_end_impl.hh @@ -1256,7 +1256,7 @@ BackEnd<Impl>::executeInsts() // ++iewExecStoreInsts; - if (!(inst->req->isLlsc())) { + if (!(inst->req->isLLSC())) { inst->setExecuted(); instToCommit(inst); diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index b30b37a22..96f3a901f 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -381,7 +381,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) } } /* - if (req->isLlsc()) { + if (req->isLLSC()) { if (req->isUncacheable()) { // Don't update result register (see stq_c in isa_desc) req->result = 2; diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index 7e7bbdb01..833aa0581 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -577,7 +577,7 @@ OzoneLSQ<Impl>::writebackStores() MemAccessResult result = dcacheInterface->access(req); //@todo temp fix for LL/SC (works fine for 1 CPU) - if (req->isLlsc()) { + if (req->isLLSC()) { req->result=1; panic("LL/SC! oh no no support!!!"); } @@ -596,7 +596,7 @@ OzoneLSQ<Impl>::writebackStores() Event *wb = NULL; /* typename IEW::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=0; wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, @@ -630,7 +630,7 @@ OzoneLSQ<Impl>::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // storeQueue[storeWBIdx].inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=1; typename BackEnd::LdWritebackEvent *wb = diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index 3ad8d1d64..6e9bb77af 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -635,7 +635,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx) PacketPtr data_pkt = new Packet(req, - (req->isLlsc() ? + (req->isLLSC() ? MemCmd::LoadLockedReq : Packet::ReadReq), Packet::Broadcast); data_pkt->dataStatic(inst->memData); @@ -662,7 +662,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx) return NoFault; } - if (req->isLlsc()) { + if (req->isLLSC()) { cpu->lockFlag = true; } diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 3943dab2d..4d290a1e9 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -589,7 +589,7 @@ OzoneLWLSQ<Impl>::writebackStores() MemCmd command = req->isSwap() ? MemCmd::SwapReq : - (req->isLlsc() ? MemCmd::WriteReq : MemCmd::StoreCondReq); + (req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); @@ -606,7 +606,7 @@ OzoneLWLSQ<Impl>::writebackStores() inst->seqNum); // @todo: Remove this SC hack once the memory system handles it. - if (req->isLlsc()) { + if (req->isLLSC()) { if (req->isUncacheable()) { req->setExtraData(2); } else { @@ -664,7 +664,7 @@ OzoneLWLSQ<Impl>::writebackStores() if (result != MA_HIT && dcacheInterface->doEvents()) { store_event->miss = true; typename BackEnd::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { wb = new typename BackEnd::LdWritebackEvent(inst, be); store_event->wbEvent = wb; @@ -691,7 +691,7 @@ OzoneLWLSQ<Impl>::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port // transaction in the 21264, but that might be // hard to accomplish in this model. |