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-rw-r--r--src/cpu/ozone/OzoneCPU.py2
-rw-r--r--src/cpu/ozone/OzoneChecker.py2
-rw-r--r--src/cpu/ozone/back_end.hh100
-rw-r--r--src/cpu/ozone/base_dyn_inst.cc4
-rw-r--r--src/cpu/ozone/cpu.hh96
-rw-r--r--src/cpu/ozone/cpu_impl.hh72
-rw-r--r--src/cpu/ozone/front_end.hh40
-rw-r--r--src/cpu/ozone/front_end_impl.hh4
-rw-r--r--src/cpu/ozone/inorder_back_end.hh16
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh3
-rw-r--r--src/cpu/ozone/inst_queue.hh32
-rw-r--r--src/cpu/ozone/lsq_unit.hh2
-rw-r--r--src/cpu/ozone/lsq_unit_impl.hh2
-rw-r--r--src/cpu/ozone/lw_back_end.hh84
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh5
-rw-r--r--src/cpu/ozone/lw_lsq.hh7
16 files changed, 179 insertions, 292 deletions
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index b9cfb448f..37386898d 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -40,8 +40,6 @@ class DerivOzoneCPU(BaseCPU):
if build_env['USE_CHECKER']:
checker = Param.BaseCPU("Checker CPU")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
index f20b8770e..bfa39ead9 100644
--- a/src/cpu/ozone/OzoneChecker.py
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -39,5 +39,3 @@ class OzoneChecker(BaseCPU):
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 4cdc86c3c..ca858ce2e 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -157,13 +157,13 @@ class BackEnd
int numInsts;
int width;
- Stats::VectorDistribution<> occ_dist;
+ Stats::VectorDistribution occ_dist;
- Stats::Vector<> inst_count;
- Stats::Vector<> peak_inst_count;
- Stats::Scalar<> empty_count;
- Stats::Scalar<> current_count;
- Stats::Scalar<> fullCount;
+ Stats::Vector inst_count;
+ Stats::Vector peak_inst_count;
+ Stats::Scalar empty_count;
+ Stats::Scalar current_count;
+ Stats::Scalar fullCount;
Stats::Formula occ_rate;
Stats::Formula avg_residency;
@@ -371,45 +371,45 @@ class BackEnd
bool fetchRedirect[Impl::MaxThreads];
// number of cycles stalled for D-cache misses
-/* Stats::Scalar<> dcacheStallCycles;
+/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
- Stats::Vector<> rob_cap_events;
- Stats::Vector<> rob_cap_inst_count;
- Stats::Vector<> iq_cap_events;
- Stats::Vector<> iq_cap_inst_count;
+ Stats::Vector rob_cap_events;
+ Stats::Vector rob_cap_inst_count;
+ Stats::Vector iq_cap_events;
+ Stats::Vector iq_cap_inst_count;
// total number of instructions executed
- Stats::Vector<> exe_inst;
- Stats::Vector<> exe_swp;
- Stats::Vector<> exe_nop;
- Stats::Vector<> exe_refs;
- Stats::Vector<> exe_loads;
- Stats::Vector<> exe_branches;
+ Stats::Vector exe_inst;
+ Stats::Vector exe_swp;
+ Stats::Vector exe_nop;
+ Stats::Vector exe_refs;
+ Stats::Vector exe_loads;
+ Stats::Vector exe_branches;
- Stats::Vector<> issued_ops;
+ Stats::Vector issued_ops;
// total number of loads forwaded from LSQ stores
- Stats::Vector<> lsq_forw_loads;
+ Stats::Vector lsq_forw_loads;
// total number of loads ignored due to invalid addresses
- Stats::Vector<> inv_addr_loads;
+ Stats::Vector inv_addr_loads;
// total number of software prefetches ignored due to invalid addresses
- Stats::Vector<> inv_addr_swpfs;
+ Stats::Vector inv_addr_swpfs;
// ready loads blocked due to memory disambiguation
- Stats::Vector<> lsq_blocked_loads;
+ Stats::Vector lsq_blocked_loads;
- Stats::Scalar<> lsqInversion;
+ Stats::Scalar lsqInversion;
- Stats::Vector<> n_issued_dist;
- Stats::VectorDistribution<> issue_delay_dist;
+ Stats::Vector n_issued_dist;
+ Stats::VectorDistribution issue_delay_dist;
- Stats::VectorDistribution<> queue_res_dist;
+ Stats::VectorDistribution queue_res_dist;
/*
- Stats::Vector<> stat_fu_busy;
- Stats::Vector2d<> stat_fuBusy;
- Stats::Vector<> dist_unissued;
- Stats::Vector2d<> stat_issued_inst_type;
+ Stats::Vector stat_fu_busy;
+ Stats::Vector2d stat_fuBusy;
+ Stats::Vector dist_unissued;
+ Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -422,34 +422,34 @@ class BackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
- Stats::Vector<> writeback_count;
- Stats::Vector<> producer_inst;
- Stats::Vector<> consumer_inst;
- Stats::Vector<> wb_penalized;
+ Stats::Vector writeback_count;
+ Stats::Vector producer_inst;
+ Stats::Vector consumer_inst;
+ Stats::Vector wb_penalized;
Stats::Formula wb_rate;
Stats::Formula wb_fanout;
Stats::Formula wb_penalized_rate;
// total number of instructions committed
- Stats::Vector<> stat_com_inst;
- Stats::Vector<> stat_com_swp;
- Stats::Vector<> stat_com_refs;
- Stats::Vector<> stat_com_loads;
- Stats::Vector<> stat_com_membars;
- Stats::Vector<> stat_com_branches;
+ Stats::Vector stat_com_inst;
+ Stats::Vector stat_com_swp;
+ Stats::Vector stat_com_refs;
+ Stats::Vector stat_com_loads;
+ Stats::Vector stat_com_membars;
+ Stats::Vector stat_com_branches;
- Stats::Distribution<> n_committed_dist;
+ Stats::Distribution n_committed_dist;
- Stats::Scalar<> commit_eligible_samples;
- Stats::Vector<> commit_eligible;
+ Stats::Scalar commit_eligible_samples;
+ Stats::Vector commit_eligible;
- Stats::Scalar<> ROB_fcount;
+ Stats::Scalar ROB_fcount;
Stats::Formula ROB_full_rate;
- Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Vector ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
- Stats::VectorDistribution<> ROB_occ_dist;
+ Stats::VectorDistribution ROB_occ_dist;
public:
void dumpInsts();
};
@@ -482,8 +482,8 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
} else {
// do functional access
@@ -524,8 +524,8 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
-// status = DcacheMissStall;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
}
}
diff --git a/src/cpu/ozone/base_dyn_inst.cc b/src/cpu/ozone/base_dyn_inst.cc
index 5a3a69dff..e0570fd16 100644
--- a/src/cpu/ozone/base_dyn_inst.cc
+++ b/src/cpu/ozone/base_dyn_inst.cc
@@ -33,7 +33,3 @@
// Explicit instantiation
template class BaseDynInst<OzoneImpl>;
-
-template <>
-int
-BaseDynInst<OzoneImpl>::instcount = 0;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index b0ea2cba9..0bfb4bfa9 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -116,10 +116,6 @@ class OzoneCPU : public BaseCPU
BaseCPU *getCpuPtr();
- void setCpuId(int id);
-
- int readCpuId() { return thread->readCpuId(); }
-
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
@@ -134,10 +130,8 @@ class OzoneCPU : public BaseCPU
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
- VirtualPort *getVirtPort(ThreadContext *tc = NULL)
- { return thread->getVirtPort(tc); }
-
- void delVirtPort(VirtualPort *vp);
+ VirtualPort *getVirtPort()
+ { return thread->getVirtPort(); }
#else
TranslatingPort *getMemPort() { return thread->getMemPort(); }
@@ -182,7 +176,7 @@ class OzoneCPU : public BaseCPU
void profileSample();
#endif
- int getThreadNum();
+ int threadId();
// Also somewhat obnoxious. Really only used for the TLB fault.
TheISA::MachInst getInst();
@@ -252,30 +246,11 @@ class OzoneCPU : public BaseCPU
bool misspeculating() { return false; }
#if !FULL_SYSTEM
- TheISA::IntReg getSyscallArg(int i)
- {
- assert(i < TheISA::NumArgumentRegs);
- return thread->renameTable[TheISA::ArgumentReg[i]]->readIntResult();
- }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, TheISA::IntReg val)
- {
- assert(i < TheISA::NumArgumentRegs);
- thread->renameTable[TheISA::ArgumentReg[i]]->setIntResult(i);
- }
-
- void setSyscallReturn(SyscallReturn return_value)
- { cpu->setSyscallReturn(return_value, thread->readTid()); }
-
Counter readFuncExeInst() { return thread->funcExeInst; }
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- { panic("Not supported on Alpha!"); }
};
// Ozone specific thread context
@@ -296,6 +271,11 @@ class OzoneCPU : public BaseCPU
// main simulation loop (one cycle)
void tick();
+#ifndef NDEBUG
+ /** Count of total number of dynamic instructions in flight. */
+ int instcount;
+#endif
+
std::set<InstSeqNum> snList;
std::set<Addr> lockAddrList;
private:
@@ -337,7 +317,7 @@ class OzoneCPU : public BaseCPU
Status _status;
public:
- void post_interrupt(int int_num, int index);
+ void wakeup();
void zero_fill_64(Addr addr) {
static int warned = 0;
@@ -358,12 +338,6 @@ class OzoneCPU : public BaseCPU
public:
BaseCPU *getCpuPtr() { return this; }
- void setCpuId(int id) { cpuId = id; }
-
- int readCpuId() { return cpuId; }
-
- int cpuId;
-
void switchOut();
void signalSwitched();
void takeOverFrom(BaseCPU *oldCPU);
@@ -416,7 +390,7 @@ class OzoneCPU : public BaseCPU
Counter startNumLoad;
// number of idle cycles
- Stats::Average<> notIdleFraction;
+ Stats::Average notIdleFraction;
Stats::Formula idleFraction;
public:
@@ -425,59 +399,20 @@ class OzoneCPU : public BaseCPU
void demapPage(Addr vaddr, uint64_t asn)
{
- itb->demap(vaddr, asn);
- dtb->demap(vaddr, asn);
+ cpu->itb->demap(vaddr, asn);
+ cpu->dtb->demap(vaddr, asn);
}
void demapInstPage(Addr vaddr, uint64_t asn)
{
- itb->demap(vaddr, asn);
+ cpu->itb->demap(vaddr, asn);
}
void demapDataPage(Addr vaddr, uint64_t asn)
{
- dtb->demap(vaddr, asn);
- }
-
-#if FULL_SYSTEM
- /** Translates instruction requestion. */
- Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return itb->translate(req, thread->getTC());
- }
-
- /** Translates data read request. */
- Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return dtb->translate(req, thread->getTC(), false);
- }
-
- /** Translates data write request. */
- Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return dtb->translate(req, thread->getTC(), true);
- }
-
-#else
- /** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
- /** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
+ cpu->dtb->demap(vaddr, asn);
}
- /** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-#endif
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(Request *req, T &data, int load_idx)
@@ -517,7 +452,6 @@ class OzoneCPU : public BaseCPU
void processInterrupts();
#else
void syscall(uint64_t &callnum);
- void setSyscallReturn(SyscallReturn return_value, int tid);
#endif
ThreadContext *tcBase() { return tc; }
@@ -539,7 +473,7 @@ class OzoneCPU : public BaseCPU
bool lockFlag;
- Stats::Scalar<> quiesceCycles;
+ Stats::Scalar quiesceCycles;
Checker<DynInstPtr> *checker;
};
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 0c7105382..aa76c8aa6 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -95,6 +95,9 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
: BaseCPU(p), thread(this, 0, p->workload[0], 0),
tickEvent(this, p->width),
#endif
+#ifndef NDEBUG
+ instcount(0),
+#endif
comm(5, 5)
{
frontEnd = new FrontEnd(p);
@@ -417,7 +420,7 @@ OzoneCPU<Impl>::init()
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(tc, tc->readCpuId());
+ TheISA::initCPU(tc, tc->contextId());
}
#endif
frontEnd->renameTable.copyFrom(thread.renameTable);
@@ -579,16 +582,14 @@ OzoneCPU<Impl>::dbg_vtophys(Addr addr)
#if FULL_SYSTEM
template <class Impl>
void
-OzoneCPU<Impl>::post_interrupt(int int_num, int index)
+OzoneCPU<Impl>::wakeup()
{
- BaseCPU::post_interrupt(int_num, index);
-
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
-// thread.activate();
+// thread.activate();
// Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call.
- activateContext(thread.readTid(), 1);
+ activateContext(thread.threadId(), 1);
}
}
#endif // FULL_SYSTEM
@@ -647,26 +648,6 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
}
-
-template <class Impl>
-void
-OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
-{
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
- if (return_value.successful()) {
- // no error
- thread.renameTable[SyscallSuccessReg]->setIntResult(0);
- thread.renameTable[ReturnValueReg]->setIntResult(
- return_value.value());
- } else {
- // got an error, return details
- thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
- thread.renameTable[ReturnValueReg]->setIntResult(
- -return_value.value());
- }
-}
#else
template <class Impl>
Fault
@@ -693,10 +674,10 @@ OzoneCPU<Impl>::processInterrupts()
// Check if there are any outstanding interrupts
//Handle the interrupts
- Fault interrupt = this->interrupts.getInterrupt(thread.getTC());
+ Fault interrupt = this->interrupts->getInterrupt(thread.getTC());
if (interrupt != NoFault) {
- this->interrupts.updateIntrInfo(thread.getTC());
+ this->interrupts->updateIntrInfo(thread.getTC());
interrupt->invoke(thread.getTC());
}
}
@@ -711,7 +692,7 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
switch (palFunc) {
case PAL::halt:
- haltContext(thread.readTid());
+ haltContext(thread.threadId());
if (--System::numSystemsRunning == 0)
exitSimLoop("all cpus halted");
break;
@@ -736,24 +717,6 @@ OzoneCPU<Impl>::OzoneTC::getCpuPtr()
template <class Impl>
void
-OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
-{
- cpu->cpuId = id;
- thread->setCpuId(id);
-}
-
-#if FULL_SYSTEM
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
-{
- vp->removeConn();
- delete vp;
-}
-#endif
-
-template <class Impl>
-void
OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
{
thread->setStatus(new_status);
@@ -763,7 +726,7 @@ template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::activate(int delay)
{
- cpu->activateContext(thread->readTid(), delay);
+ cpu->activateContext(thread->threadId(), delay);
}
/// Set the status to Suspended.
@@ -771,7 +734,7 @@ template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::suspend()
{
- cpu->suspendContext(thread->readTid());
+ cpu->suspendContext(thread->threadId());
}
/// Set the status to Unallocated.
@@ -779,7 +742,7 @@ template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
{
- cpu->deallocateContext(thread->readTid(), delay);
+ cpu->deallocateContext(thread->threadId(), delay);
}
/// Set the status to Halted.
@@ -787,7 +750,7 @@ template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::halt()
{
- cpu->haltContext(thread->readTid());
+ cpu->haltContext(thread->threadId());
}
#if FULL_SYSTEM
@@ -813,7 +776,8 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
// copy over functional state
setStatus(old_context->status());
copyArchRegs(old_context);
- setCpuId(old_context->readCpuId());
+ setCpuId(old_context->cpuId());
+ setContextId(old_context->contextId());
thread->setInst(old_context->getInst());
#if !FULL_SYSTEM
@@ -901,9 +865,9 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
template <class Impl>
int
-OzoneCPU<Impl>::OzoneTC::getThreadNum()
+OzoneCPU<Impl>::OzoneTC::threadId()
{
- return thread->readTid();
+ return thread->threadId();
}
template <class Impl>
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 667392c06..38fc89e3f 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -275,48 +275,48 @@ class FrontEnd
private:
// number of idle cycles
/*
- Stats::Average<> notIdleFraction;
+ Stats::Average notIdleFraction;
Stats::Formula idleFraction;
*/
// @todo: Consider making these vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */
- Stats::Scalar<> icacheStallCycles;
+ Stats::Scalar icacheStallCycles;
/** Stat for total number of fetched instructions. */
- Stats::Scalar<> fetchedInsts;
- Stats::Scalar<> fetchedBranches;
+ Stats::Scalar fetchedInsts;
+ Stats::Scalar fetchedBranches;
/** Stat for total number of predicted branches. */
- Stats::Scalar<> predictedBranches;
+ Stats::Scalar predictedBranches;
/** Stat for total number of cycles spent fetching. */
- Stats::Scalar<> fetchCycles;
+ Stats::Scalar fetchCycles;
- Stats::Scalar<> fetchIdleCycles;
+ Stats::Scalar fetchIdleCycles;
/** Stat for total number of cycles spent squashing. */
- Stats::Scalar<> fetchSquashCycles;
+ Stats::Scalar fetchSquashCycles;
/** Stat for total number of cycles spent blocked due to other stages in
* the pipeline.
*/
- Stats::Scalar<> fetchBlockedCycles;
+ Stats::Scalar fetchBlockedCycles;
/** Stat for total number of fetched cache lines. */
- Stats::Scalar<> fetchedCacheLines;
+ Stats::Scalar fetchedCacheLines;
- Stats::Scalar<> fetchIcacheSquashes;
+ Stats::Scalar fetchIcacheSquashes;
/** Distribution of number of instructions fetched each cycle. */
- Stats::Distribution<> fetchNisnDist;
-// Stats::Vector<> qfull_iq_occupancy;
-// Stats::VectorDistribution<> qfull_iq_occ_dist_;
+ Stats::Distribution fetchNisnDist;
+// Stats::Vector qfull_iq_occupancy;
+// Stats::VectorDistribution qfull_iq_occ_dist_;
Stats::Formula idleRate;
Stats::Formula branchRate;
Stats::Formula fetchRate;
- Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
+ Stats::Scalar IFQCount; // cumulative IFQ occupancy
Stats::Formula IFQOccupancy;
Stats::Formula IFQLatency;
- Stats::Scalar<> IFQFcount; // cumulative IFQ full count
+ Stats::Scalar IFQFcount; // cumulative IFQ full count
Stats::Formula IFQFullRate;
- Stats::Scalar<> dispatchCountStat;
- Stats::Scalar<> dispatchedSerializing;
- Stats::Scalar<> dispatchedTempSerializing;
- Stats::Scalar<> dispatchSerializeStallCycles;
+ Stats::Scalar dispatchCountStat;
+ Stats::Scalar dispatchedSerializing;
+ Stats::Scalar dispatchedTempSerializing;
+ Stats::Scalar dispatchSerializeStallCycles;
Stats::Formula dispatchRate;
Stats::Formula regIntFull;
Stats::Formula regFpFull;
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 198ce0308..6b47ef539 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -477,10 +477,10 @@ FrontEnd<Impl>::fetchCacheLine()
// Setup the memReq to do a read of the first isntruction's address.
// Set the appropriate read size and flags as well.
memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
- PC, cpu->readCpuId(), 0);
+ PC, cpu->thread->contextId());
// Translate the instruction request.
- fault = cpu->translateInstReq(memReq, thread);
+ fault = cpu->itb->translateAtomic(memReq, thread);
// Now do the timing access to see whether or not the instruction
// exists within the cache.
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index aef29b1e2..e930144be 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -192,7 +192,7 @@ class InorderBackEnd
TimeBuffer<CommStruct> *comm;
// number of cycles stalled for D-cache misses
- Stats::Scalar<> dcacheStallCycles;
+ Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
};
@@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault fault = cpu->translateDataReadReq(memReq);
+ Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
// if we have a cache, do cache access too
if (fault == NoFault && dcacheInterface) {
@@ -222,7 +222,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
// are executed twice.
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -245,11 +245,11 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault fault = cpu->translateDataWriteReq(memReq);
+ Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;
-// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
+// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->flags &= ~INST_READ;
@@ -261,7 +261,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (result != MA_HIT) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -307,7 +307,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss load stall!\n");
} else {
@@ -372,7 +372,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
-// unscheduleTickEvent();
+// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss store stall!\n");
} else {
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index cf8634a42..798b628d6 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -149,8 +149,7 @@ InorderBackEnd<Impl>::tick()
// if (interrupt) then set thread PC, stall front end, record that
// I'm waiting for it to drain. (for now just squash)
#if FULL_SYSTEM
- if (interruptBlocked ||
- cpu->check_interrupts(tc)) {
+ if (interruptBlocked || cpu->checkInterrupts(tc)) {
if (!robEmpty()) {
interruptBlocked = true;
//AlphaDep
diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh
index a11d5204b..e840d5c21 100644
--- a/src/cpu/ozone/inst_queue.hh
+++ b/src/cpu/ozone/inst_queue.hh
@@ -473,35 +473,35 @@ class InstQueue
void dumpInsts();
/** Stat for number of instructions added. */
- Stats::Scalar<> iqInstsAdded;
+ Stats::Scalar iqInstsAdded;
/** Stat for number of non-speculative instructions added. */
- Stats::Scalar<> iqNonSpecInstsAdded;
-// Stats::Scalar<> iqIntInstsAdded;
+ Stats::Scalar iqNonSpecInstsAdded;
+// Stats::Scalar iqIntInstsAdded;
/** Stat for number of integer instructions issued. */
- Stats::Scalar<> iqIntInstsIssued;
-// Stats::Scalar<> iqFloatInstsAdded;
+ Stats::Scalar iqIntInstsIssued;
+// Stats::Scalar iqFloatInstsAdded;
/** Stat for number of floating point instructions issued. */
- Stats::Scalar<> iqFloatInstsIssued;
-// Stats::Scalar<> iqBranchInstsAdded;
+ Stats::Scalar iqFloatInstsIssued;
+// Stats::Scalar iqBranchInstsAdded;
/** Stat for number of branch instructions issued. */
- Stats::Scalar<> iqBranchInstsIssued;
-// Stats::Scalar<> iqMemInstsAdded;
+ Stats::Scalar iqBranchInstsIssued;
+// Stats::Scalar iqMemInstsAdded;
/** Stat for number of memory instructions issued. */
- Stats::Scalar<> iqMemInstsIssued;
-// Stats::Scalar<> iqMiscInstsAdded;
+ Stats::Scalar iqMemInstsIssued;
+// Stats::Scalar iqMiscInstsAdded;
/** Stat for number of miscellaneous instructions issued. */
- Stats::Scalar<> iqMiscInstsIssued;
+ Stats::Scalar iqMiscInstsIssued;
/** Stat for number of squashed instructions that were ready to issue. */
- Stats::Scalar<> iqSquashedInstsIssued;
+ Stats::Scalar iqSquashedInstsIssued;
/** Stat for number of squashed instructions examined when squashing. */
- Stats::Scalar<> iqSquashedInstsExamined;
+ Stats::Scalar iqSquashedInstsExamined;
/** Stat for number of squashed instruction operands examined when
* squashing.
*/
- Stats::Scalar<> iqSquashedOperandsExamined;
+ Stats::Scalar iqSquashedOperandsExamined;
/** Stat for number of non-speculative instructions removed due to a squash.
*/
- Stats::Scalar<> iqSquashedNonSpecRemoved;
+ Stats::Scalar iqSquashedNonSpecRemoved;
};
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 981682c26..47be245e5 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -331,7 +331,7 @@ class OzoneLSQ {
//list<InstSeqNum> mshrSeqNums;
- //Stats::Scalar<> dcacheStallCycles;
+ //Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
/** Wire to read information from the issue stage time queue. */
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index 84a90eede..c24410520 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -553,7 +553,7 @@ OzoneLSQ<Impl>::writebackStores()
MemReqPtr req = storeQueue[storeWBIdx].req;
storeQueue[storeWBIdx].committed = true;
-// Fault fault = cpu->translateDataReadReq(req);
+// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Write;
req->completionEvent = NULL;
req->time = curTick;
diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index a335ab7dc..4a1657c9b 100644
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -326,47 +326,47 @@ class LWBackEnd
bool exactFullStall;
// number of cycles stalled for D-cache misses
-/* Stats::Scalar<> dcacheStallCycles;
+/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
- Stats::Vector<> robCapEvents;
- Stats::Vector<> robCapInstCount;
- Stats::Vector<> iqCapEvents;
- Stats::Vector<> iqCapInstCount;
+ Stats::Vector robCapEvents;
+ Stats::Vector robCapInstCount;
+ Stats::Vector iqCapEvents;
+ Stats::Vector iqCapInstCount;
// total number of instructions executed
- Stats::Vector<> exeInst;
- Stats::Vector<> exeSwp;
- Stats::Vector<> exeNop;
- Stats::Vector<> exeRefs;
- Stats::Vector<> exeLoads;
- Stats::Vector<> exeBranches;
+ Stats::Vector exeInst;
+ Stats::Vector exeSwp;
+ Stats::Vector exeNop;
+ Stats::Vector exeRefs;
+ Stats::Vector exeLoads;
+ Stats::Vector exeBranches;
- Stats::Vector<> issuedOps;
+ Stats::Vector issuedOps;
// total number of loads forwaded from LSQ stores
- Stats::Vector<> lsqForwLoads;
+ Stats::Vector lsqForwLoads;
// total number of loads ignored due to invalid addresses
- Stats::Vector<> invAddrLoads;
+ Stats::Vector invAddrLoads;
// total number of software prefetches ignored due to invalid addresses
- Stats::Vector<> invAddrSwpfs;
+ Stats::Vector invAddrSwpfs;
// ready loads blocked due to memory disambiguation
- Stats::Vector<> lsqBlockedLoads;
+ Stats::Vector lsqBlockedLoads;
- Stats::Scalar<> lsqInversion;
+ Stats::Scalar lsqInversion;
- Stats::Vector<> nIssuedDist;
+ Stats::Vector nIssuedDist;
/*
- Stats::VectorDistribution<> issueDelayDist;
+ Stats::VectorDistribution issueDelayDist;
- Stats::VectorDistribution<> queueResDist;
+ Stats::VectorDistribution queueResDist;
*/
/*
- Stats::Vector<> stat_fu_busy;
- Stats::Vector2d<> stat_fuBusy;
- Stats::Vector<> dist_unissued;
- Stats::Vector2d<> stat_issued_inst_type;
+ Stats::Vector stat_fu_busy;
+ Stats::Vector2d stat_fuBusy;
+ Stats::Vector dist_unissued;
+ Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -379,37 +379,37 @@ class LWBackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
- Stats::Vector<> writebackCount;
- Stats::Vector<> producerInst;
- Stats::Vector<> consumerInst;
- Stats::Vector<> wbPenalized;
+ Stats::Vector writebackCount;
+ Stats::Vector producerInst;
+ Stats::Vector consumerInst;
+ Stats::Vector wbPenalized;
Stats::Formula wbRate;
Stats::Formula wbFanout;
Stats::Formula wbPenalizedRate;
// total number of instructions committed
- Stats::Vector<> statComInst;
- Stats::Vector<> statComSwp;
- Stats::Vector<> statComRefs;
- Stats::Vector<> statComLoads;
- Stats::Vector<> statComMembars;
- Stats::Vector<> statComBranches;
+ Stats::Vector statComInst;
+ Stats::Vector statComSwp;
+ Stats::Vector statComRefs;
+ Stats::Vector statComLoads;
+ Stats::Vector statComMembars;
+ Stats::Vector statComBranches;
- Stats::Distribution<> nCommittedDist;
+ Stats::Distribution nCommittedDist;
- Stats::Scalar<> commitEligibleSamples;
- Stats::Vector<> commitEligible;
+ Stats::Scalar commitEligibleSamples;
+ Stats::Vector commitEligible;
- Stats::Vector<> squashedInsts;
- Stats::Vector<> ROBSquashedInsts;
+ Stats::Vector squashedInsts;
+ Stats::Vector ROBSquashedInsts;
- Stats::Scalar<> ROBFcount;
+ Stats::Scalar ROBFcount;
Stats::Formula ROBFullRate;
- Stats::Vector<> ROBCount; // cumulative ROB occupancy
+ Stats::Vector ROBCount; // cumulative ROB occupancy
Stats::Formula ROBOccRate;
-// Stats::VectorDistribution<> ROBOccDist;
+// Stats::VectorDistribution ROBOccDist;
public:
void dumpInsts();
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index a5d79a789..60c42edd3 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -525,10 +525,7 @@ template <class Impl>
void
LWBackEnd<Impl>::checkInterrupts()
{
- if (cpu->checkInterrupts &&
- cpu->check_interrupts(tc) &&
- !trapSquash &&
- !tcSquash) {
+ if (cpu->checkInterrupts(tc) && !trapSquash && !tcSquash) {
frontEnd->interruptPending = true;
if (robEmpty() && !LSQ.hasStoresToWB()) {
// Will need to squash all instructions currently in flight and have
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 7fc8b6307..4f8101bc0 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -39,6 +39,7 @@
#include "arch/faults.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "mem/packet.hh"
@@ -301,7 +302,7 @@ class OzoneLWLSQ {
};
/** Derived class to hold any sender state the LSQ needs. */
- class LSQSenderState : public Packet::SenderState
+ class LSQSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Default constructor. */
@@ -410,9 +411,9 @@ class OzoneLWLSQ {
//list<InstSeqNum> mshrSeqNums;
/** Tota number of memory ordering violations. */
- Stats::Scalar<> lsqMemOrderViolation;
+ Stats::Scalar lsqMemOrderViolation;
- //Stats::Scalar<> dcacheStallCycles;
+ //Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// Make these per thread?
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 14:31:04 +0000