diff options
Diffstat (limited to 'src/cpu/pred/bpred_unit.cc')
-rw-r--r-- | src/cpu/pred/bpred_unit.cc | 146 |
1 files changed, 38 insertions, 108 deletions
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index 04a05eaa4..8bb84f836 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -59,18 +59,8 @@ BPredUnit::BPredUnit(const Params *params) predHist(numThreads), BTB(params->BTBEntries, params->BTBTagSize, - params->instShiftAmt, - params->numThreads), + params->instShiftAmt), RAS(numThreads), - useIndirect(params->useIndirect), - iPred(params->indirectHashGHR, - params->indirectHashTargets, - params->indirectSets, - params->indirectWays, - params->indirectTagSize, - params->indirectPathLength, - params->instShiftAmt, - params->numThreads), instShiftAmt(params->instShiftAmt) { for (auto& r : RAS) @@ -126,27 +116,6 @@ BPredUnit::regStats() .name(name() + ".RASInCorrect") .desc("Number of incorrect RAS predictions.") ; - - indirectLookups - .name(name() + ".indirectLookups") - .desc("Number of indirect predictor lookups.") - ; - - indirectHits - .name(name() + ".indirectHits") - .desc("Number of indirect target hits.") - ; - - indirectMisses - .name(name() + ".indirectMisses") - .desc("Number of indirect misses.") - ; - - indirectMispredicted - .name(name() + "indirectMispredcited") - .desc("Number of mispredicted indirect branches.") - ; - } ProbePoints::PMUUPtr @@ -195,10 +164,10 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, DPRINTF(Branch, "[tid:%i]: Unconditional control.\n", tid); pred_taken = true; // Tell the BP there was an unconditional branch. - uncondBranch(tid, pc.instAddr(), bp_history); + uncondBranch(pc.instAddr(), bp_history); } else { ++condPredicted; - pred_taken = lookup(tid, pc.instAddr(), bp_history); + pred_taken = lookup(pc.instAddr(), bp_history); DPRINTF(Branch, "[tid:%i]: [sn:%i] Branch predictor" " predicted %i for PC %s\n", tid, seqNum, pred_taken, pc); @@ -246,59 +215,31 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, tid, pc, pc, RAS[tid].topIdx()); } - if (inst->isDirectCtrl() || !useIndirect) { - // Check BTB on direct branches - if (BTB.valid(pc.instAddr(), tid)) { - ++BTBHits; - - // If it's not a return, use the BTB to get target addr. - target = BTB.lookup(pc.instAddr(), tid); - - DPRINTF(Branch, "[tid:%i]: Instruction %s predicted" - " target is %s.\n", tid, pc, target); - - } else { - DPRINTF(Branch, "[tid:%i]: BTB doesn't have a " - "valid entry.\n",tid); - pred_taken = false; - // The Direction of the branch predictor is altered - // because the BTB did not have an entry - // The predictor needs to be updated accordingly - if (!inst->isCall() && !inst->isReturn()) { - btbUpdate(tid, pc.instAddr(), bp_history); - DPRINTF(Branch, "[tid:%i]:[sn:%i] btbUpdate" - " called for %s\n", tid, seqNum, pc); - } else if (inst->isCall() && !inst->isUncondCtrl()) { - RAS[tid].pop(); - predict_record.pushedRAS = false; - } - TheISA::advancePC(target, inst); - } + if (BTB.valid(pc.instAddr(), tid)) { + ++BTBHits; + + // If it's not a return, use the BTB to get the target addr. + target = BTB.lookup(pc.instAddr(), tid); + + DPRINTF(Branch, "[tid:%i]: Instruction %s predicted" + " target is %s.\n", tid, pc, target); + } else { - predict_record.wasIndirect = true; - ++indirectLookups; - //Consult indirect predictor on indirect control - if (iPred.lookup(pc.instAddr(), getGHR(tid, bp_history), - target, tid)) { - // Indirect predictor hit - ++indirectHits; - DPRINTF(Branch, "[tid:%i]: Instruction %s predicted " - "indirect target is %s.\n", tid, pc, target); - } else { - ++indirectMisses; - pred_taken = false; - DPRINTF(Branch, "[tid:%i]: Instruction %s no indirect " - "target.\n", tid, pc); - if (!inst->isCall() && !inst->isReturn()) { - - } else if (inst->isCall() && !inst->isUncondCtrl()) { - RAS[tid].pop(); - predict_record.pushedRAS = false; - } - TheISA::advancePC(target, inst); + DPRINTF(Branch, "[tid:%i]: BTB doesn't have a " + "valid entry.\n",tid); + pred_taken = false; + // The Direction of the branch predictor is altered because the + // BTB did not have an entry + // The predictor needs to be updated accordingly + if (!inst->isCall() && !inst->isReturn()) { + btbUpdate(pc.instAddr(), bp_history); + DPRINTF(Branch, "[tid:%i]:[sn:%i] btbUpdate" + " called for %s\n", tid, seqNum, pc); + } else if (inst->isCall() && !inst->isUncondCtrl()) { + RAS[tid].pop(); + predict_record.pushedRAS = false; } - iPred.recordIndirect(pc.instAddr(), target.instAddr(), seqNum, - tid); + TheISA::advancePC(target, inst); } } } else { @@ -346,7 +287,7 @@ BPredUnit::predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum, DPRINTF(Branch, "[tid:%i] Unconditional control.\n", tid); pred_taken = true; // Tell the BP there was an unconditional branch. - uncondBranch(tid, instPC.instAddr(), bp_history); + uncondBranch(instPC.instAddr(), bp_history); if (inst->isReturn() && RAS[tid].empty()) { DPRINTF(Branch, "[tid:%i] RAS is empty, predicting " @@ -356,7 +297,7 @@ BPredUnit::predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum, } else { ++condPredicted; - pred_taken = lookup(tid, predPC.instAddr(), bp_history); + pred_taken = lookup(predPC.instAddr(), bp_history); } PredictorHistory predict_record(seqNum, predPC.instAddr(), pred_taken, @@ -446,16 +387,14 @@ BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid) DPRINTF(Branch, "[tid:%i]: Committing branches until " "[sn:%lli].\n", tid, done_sn); - iPred.commit(done_sn, tid); while (!predHist[tid].empty() && predHist[tid].back().seqNum <= done_sn) { // Update the branch predictor with the correct results. if (!predHist[tid].back().wasSquashed) { - update(tid, predHist[tid].back().pc, - predHist[tid].back().predTaken, - predHist[tid].back().bpHistory, false); + update(predHist[tid].back().pc, predHist[tid].back().predTaken, + predHist[tid].back().bpHistory, false); } else { - retireSquashed(tid, predHist[tid].back().bpHistory); + retireSquashed(predHist[tid].back().bpHistory); } predHist[tid].pop_back(); @@ -467,7 +406,6 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid) { History &pred_hist = predHist[tid]; - iPred.squash(squashed_sn, tid); while (!pred_hist.empty() && pred_hist.front().seqNum > squashed_sn) { if (pred_hist.front().usedRAS) { @@ -486,7 +424,7 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid) } // This call should delete the bpHistory. - squash(tid, pred_hist.front().bpHistory); + squash(pred_hist.front().bpHistory); DPRINTF(Branch, "[tid:%i]: Removing history for [sn:%i] " "PC %s.\n", tid, pred_hist.front().seqNum, @@ -546,14 +484,9 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, if ((*hist_it).usedRAS) { ++RASIncorrect; - DPRINTF(Branch, "[tid:%i]: Incorrect RAS [sn:%i]\n", - tid, hist_it->seqNum); } - // Have to get GHR here because the update deletes bpHistory - unsigned ghr = getGHR(tid, hist_it->bpHistory); - - update(tid, (*hist_it).pc, actually_taken, + update((*hist_it).pc, actually_taken, pred_hist.front().bpHistory, true); hist_it->wasSquashed = true; @@ -565,15 +498,12 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, RAS[tid].pop(); hist_it->usedRAS = true; } - if (hist_it->wasIndirect) { - ++indirectMispredicted; - iPred.recordTarget(hist_it->seqNum, ghr, corrTarget, tid); - } else { - DPRINTF(Branch,"[tid: %i] BTB Update called for [sn:%i]" - " PC: %s\n", tid,hist_it->seqNum, hist_it->pc); - BTB.update((*hist_it).pc, corrTarget, tid); - } + DPRINTF(Branch,"[tid: %i] BTB Update called for [sn:%i]" + " PC: %s\n", tid,hist_it->seqNum, hist_it->pc); + + BTB.update((*hist_it).pc, corrTarget, tid); + } else { //Actually not Taken if (hist_it->usedRAS) { |