1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/reg_class_impl.hh b/src/cpu/reg_class_impl.hh
index a47328b10..98b341e86 100644
--- a/src/cpu/reg_class_impl.hh
+++ b/src/cpu/reg_class_impl.hh
@@ -55,13 +55,18 @@ bool RegId::isZeroReg() const
              regIdx == TheISA::ZeroReg));
 }
 
+static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
+
 RegIndex RegId::flatIndex() const {
     switch (regClass) {
     case IntRegClass:
     case FloatRegClass:
+    case VecRegClass:
     case CCRegClass:
     case MiscRegClass:
         return regIdx;
+    case VecElemClass:
+        return Scale*regIdx + elemIdx;
     }
     panic("Trying to flatten a register without class!");
     return -1;