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Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 93cd02ba7..1199f35e1 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -34,4 +34,4 @@ class AtomicSimpleCPU(BaseSimpleCPU): width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") - physmem_port = Port("Physical Memory Port") + physmem_port = MasterPort("Physical Memory Port") |