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-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 3d72f4098..a4d807f86 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,5 +37,5 @@ class AtomicSimpleCPU(BaseSimpleCPU):
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
- _mem_ports = BaseSimpleCPU._mem_ports + \
- ['icache_port', 'dcache_port', 'physmem_port']
+ _cached_ports = BaseSimpleCPU._cached_ports + \
+ ['icache_port', 'dcache_port']