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Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index a0b358439..e1c1e4cd1 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -28,9 +28,9 @@ from m5.params import * from m5 import build_env -from BaseCPU import BaseCPU +from BaseSimpleCPU import BaseSimpleCPU -class AtomicSimpleCPU(BaseCPU): +class AtomicSimpleCPU(BaseSimpleCPU): type = 'AtomicSimpleCPU' width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") @@ -42,5 +42,5 @@ class AtomicSimpleCPU(BaseCPU): icache_port = Port("Instruction Port") dcache_port = Port("Data Port") physmem_port = Port("Physical Memory Port") - _mem_ports = BaseCPU._mem_ports + \ + _mem_ports = BaseSimpleCPU._mem_ports + \ ['icache_port', 'dcache_port', 'physmem_port'] |