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-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 54daaec63..1927a5862 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU
class AtomicSimpleCPU(BaseSimpleCPU):
type = 'AtomicSimpleCPU'
+ cxx_header = "cpu/simple/atomic.hh"
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")