summaryrefslogtreecommitdiff
path: root/src/cpu/simple/BaseSimpleCPU.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/simple/BaseSimpleCPU.py')
-rw-r--r--src/cpu/simple/BaseSimpleCPU.py18
1 files changed, 11 insertions, 7 deletions
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index ea2c642e6..d9b963890 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -29,15 +29,19 @@
from m5.defines import buildEnv
from m5.params import *
from BaseCPU import BaseCPU
-
-if buildEnv['USE_CHECKER']:
- from DummyChecker import DummyChecker
+from DummyChecker import DummyChecker
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
abstract = True
- if buildEnv['USE_CHECKER']:
- checker = Param.BaseCPU(DummyChecker(), "checker")
- checker.itb = BaseCPU.itb
- checker.dtb = BaseCPU.dtb
+ def addCheckerCpu(self):
+ if buildEnv['TARGET_ISA'] in ['arm']:
+ from ArmTLB import ArmTLB
+
+ self.checker = DummyChecker(workload = self.workload)
+ self.checker.itb = ArmTLB(size = self.itb.size)
+ self.checker.dtb = ArmTLB(size = self.dtb.size)
+ else:
+ print "ERROR: Checker only supported under ARM ISA!"
+ exit(1)