summaryrefslogtreecommitdiff
path: root/src/cpu/simple/BaseSimpleCPU.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/simple/BaseSimpleCPU.py')
-rw-r--r--src/cpu/simple/BaseSimpleCPU.py9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index b40458482..6714295d2 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -30,9 +30,10 @@ from __future__ import print_function
from m5.defines import buildEnv
from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
@@ -41,7 +42,7 @@ class BaseSimpleCPU(BaseCPU):
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from ArmTLB import ArmTLB
+ from m5.objects.ArmTLB import ArmTLB
self.checker = DummyChecker(workload = self.workload)
self.checker.itb = ArmTLB(size = self.itb.size)