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Diffstat (limited to 'src/cpu/simple/TimingSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 6b83c41aa..8d6888f72 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port'] + _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port'] |