diff options
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 06f52e30e..9187fa7c7 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -254,7 +254,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) notIdleFraction++; //Make sure ticks are still on multiples of cycles - tickEvent.schedule(nextCycle(curTick + cycles(delay))); + tickEvent.schedule(nextCycle(curTick + ticks(delay))); _status = Running; } @@ -584,7 +584,7 @@ AtomicSimpleCPU::tick() { DPRINTF(SimpleCPU, "Tick\n"); - Tick latency = cycles(1); // instruction takes one cycle by default + Tick latency = ticks(1); // instruction takes one cycle by default for (int i = 0; i < width; ++i) { numCycles++; @@ -642,14 +642,14 @@ AtomicSimpleCPU::tick() if (simulate_stalls) { Tick icache_stall = - icache_access ? icache_latency - cycles(1) : 0; + icache_access ? icache_latency - ticks(1) : 0; Tick dcache_stall = - dcache_access ? dcache_latency - cycles(1) : 0; - Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); - if (cycles(stall_cycles) < (icache_stall + dcache_stall)) - latency += cycles(stall_cycles+1); + dcache_access ? dcache_latency - ticks(1) : 0; + Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1); + if (ticks(stall_cycles) < (icache_stall + dcache_stall)) + latency += ticks(stall_cycles+1); else - latency += cycles(stall_cycles); + latency += ticks(stall_cycles); } } |